View source for 00017920 - 00017b48

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 00017920: 27bdffe8 addiu r29,r29,0xffe8
 00017924: 3c028003 lui r2,0x8003
 00017928: 84422a54 lh r2,0x2a54(r2)
 0001792c: 00801821 addu r3,r4,r0
 00017930: 04400082 bltz r2,0x00017b3c
 00017934: afbf0010 sw r31,0x0010(r29)
 00017938: 3c058004 lui r5,0x8004
 0001793c: 24a508e0 addiu r5,r5,0x08e0            start of SPU malloc table == 800408e0
 00017940: 34628000 ori r2,r3,0x8000
 00017944: 3c018003 lui r1,0x8003
 00017948: a4222a54 sh r2,0x2a54(r1)
 0001794c: 0c006531 jal 0x000194c4                [[SpuInitMalloc]]
 00017950: 34040006 ori r4,r0,0x0006              maximum 6 allocations
 00017954: 3c048003 lui r4,0x8003
 00017958: 248470bc addiu r4,r4,0x70bc
 0001795c: 0c00508f jal 0x0001423c
 00017960: 34058000 ori r5,r0,0x8000
 00017964: 0c005151 jal 0x00014544
 00017968: 00000000 nop
 0001796c: 3c021234 lui r2,0x1234
 00017970: 34425678 ori r2,r2,0x5678
 00017974: 3c018003 lui r1,0x8003
 00017978: ac222a18 sw r2,0x2a18(r1)
 0001797c: 3c018003 lui r1,0x8003
 00017980: ac202a50 sw r0,0x2a50(r1)
 00017984: 3c018003 lui r1,0x8003
 00017988: ac202a60 sw r0,0x2a60(r1)
 0001798c: 3c018003 lui r1,0x8003
 00017990: ac202a00 sw r0,0x2a00(r1)
 00017994: 3c018003 lui r1,0x8003
 00017998: ac202a44 sw r0,0x2a44(r1)
 0001799c: 3c018003 lui r1,0x8003
 000179a0: ac202a0c sw r0,0x2a0c(r1)
 000179a4: 3c018003 lui r1,0x8003
 000179a8: ac202a10 sw r0,0x2a10(r1)
 000179ac: 3c018003 lui r1,0x8003
 000179b0: ac202a14 sw r0,0x2a14(r1)
 000179b4: 3c018003 lui r1,0x8003
 000179b8: ac202a08 sw r0,0x2a08(r1)
 000179bc: 3c018003 lui r1,0x8003
 000179c0: ac202a20 sw r0,0x2a20(r1)
 000179c4: 3c018003 lui r1,0x8003
 000179c8: a4202a1c sh r0,0x2a1c(r1)
 000179cc: 3c018003 lui r1,0x8003
 000179d0: a4202a58 sh r0,0x2a58(r1)
 000179d4: 0c004d8f jal 0x0001363c
 000179d8: 00000000 nop
 000179dc: 3c018003 lui r1,0x8003
 000179e0: ac222a60 sw r2,0x2a60(r1)
 000179e4: 3402000c ori r2,r0,0x000c
 000179e8: 3c018003 lui r1,0x8003
 000179ec: a4207028 sh r0,0x7028(r1)
 000179f0: 3c018003 lui r1,0x8003
 000179f4: a420702a sh r0,0x702a(r1)
 000179f8: 3c018003 lui r1,0x8003
 000179fc: ac227020 sw r2,0x7020(r1)
 00017a00: 0c00880d jal 0x00022034                 [[Enter Critical Section]]
 00017a04: 00000000 nop
 00017a08: 3c04f200 lui r4,0xf200
 00017a0c: 34840002 ori r4,r4,0x0002               cause descriptor 0xf2000002 root counter 2
 00017a10: 34050002 ori r5,r0,0x0002               spec = timer
 00017a14: 3c078001 lui r7,0x8001
 00017a18: 24e749dc addiu r7,r7,0x49dc             event handler == [[000149dc - 00014f14]]
 00017a1c: 0c0087dd jal 0x00021f74                 [[OpenEvent]]
 00017a20: 34061000 ori r6,r0,0x1000               mode == execute function
 00017a24: 3c04f000 lui r4,0xf000
 00017a28: 34840009 ori r4,r4,0x0009               cause descriptor 0xf0000009 IRQ 9 SPU
 00017a2c: 34051000 ori r5,r0,0x1000               spec = IRQ 
 00017a30: 3c078002 lui r7,0x8002
 00017a34: 24e78510 addiu r7,r7,0x8510             event handler == 80028510 partway through [[unpack packet]]
 00017a38: 3c018003 lui r1,0x8003
 00017a3c: ac222a5c sw r2,0x2a5c(r1)               store event descriptor
 00017a40: 0c0087dd jal 0x00021f74                 [[OpenEvent]]
 00017a44: 34061000 ori r6,r0,0x1000               mode == execute function
 00017a48: 3c04f200 lui r4,0xf200
 00017a4c: 34840002 ori r4,r4,0x0002               root counter == 0xf2000002 root counter 2
 00017a50: 340544e8 ori r5,r0,0x44e8               target value 44e8
 00017a54: 3c018003 lui r1,0x8003
 00017a58: ac222a48 sw r2,0x2a48(r1)               store event descriptor
 00017a5c: 3c018003 lui r1,0x8003
 00017a60: ac202a2c sw r0,0x2a2c(r1)
 00017a64: 3c018003 lui r1,0x8003
 00017a68: ac202a34 sw r0,0x2a34(r1)
 00017a6c: 0c008845 jal 0x00022114                 [[SetRCnt]]
 00017a70: 34061000 ori r6,r0,0x1000               mode == execute function
 00017a74: 3c04f200 lui r4,0xf200
 00017a78: 0c00887b jal 0x000221ec                 [[StartRCnt]]
 00017a7c: 34840002 ori r4,r4,0x0002               start root counter 2
 00017a80: 3c048003 lui r4,0x8003
 00017a84: 8c842a5c lw r4,0x2a5c(r4)
 00017a88: 0c0087ed jal 0x00021fb4                 [[EnableEvent]]
 00017a8c: 00000000 nop
 00017a90: 3c048002 lui r4,0x8002
 00017a94: 248484f0 addiu r4,r4,0x84f0             0x800284f0 (partway through [[Unpack packet]]
 00017a98: 0c006c13 jal 0x0001b04c                 [[SpuSetTransferCallback]]
 00017a9c: 00000000 nop
 00017aa0: 3c028003 lui r2,0x8003
 00017aa4: 94422a54 lhu r2,0x2a54(r2)
 00017aa8: 00000000 nop
 00017aac: 34420001 ori r2,r2,0x0001
 00017ab0: 3c018003 lui r1,0x8003
 00017ab4: a4222a54 sh r2,0x2a54(r1)
 00017ab8: 0c008811 jal 0x00022044                 [[Exit Critical Section]]
 00017abc: 00000000 nop
 00017ac0: 0c005fdb jal 0x00017f6c                 
 00017ac4: 34040001 ori r4,r0,0x0001
 00017ac8: 34040004 ori r4,r0,0x0004
 00017acc: 00002821 addu r5,r0,r0
 00017ad0: 00003021 addu r6,r0,r0
 00017ad4: 2402ffff addiu r2,r0,0xffff
 00017ad8: 3c018003 lui r1,0x8003
 00017adc: ac22700c sw r2,0x700c(r1)
 00017ae0: 0c006050 jal 0x00018140
 00017ae4: 00003821 addu r7,r0,r0
 00017ae8: 00002021 addu r4,r0,r0
 00017aec: 0c0060f0 jal 0x000183c0
 00017af0: 34050001 ori r5,r0,0x0001
 00017af4: 34043fff ori r4,r0,0x3fff
 00017af8: 0c006090 jal 0x00018240
 00017afc: 00002821 addu r5,r0,r0
 00017b00: 34046400 ori r4,r0,0x6400
 00017b04: 0c0060c0 jal 0x00018300
 00017b08: 00002821 addu r5,r0,r0
 00017b0c: 3c028003 lui r2,0x8003
 00017b10: 94422a54 lhu r2,0x2a54(r2)
 00017b14: 00000000 nop
 00017b18: 30422000 andi r2,r2,0x2000
 00017b1c: 10400003 beq r2,r0,0x00017b2c
 00017b20: 00000000 nop
 00017b24: 0c006024 jal 0x00018090
 00017b28: 340400c0 ori r4,r0,0x00c0
 00017b2c: 0c004933 jal 0x000124cc
 00017b30: 34040001 ori r4,r0,0x0001
 00017b34: 3c018003 lui r1,0x8003
 00017b38: a4202a28 sh r0,0x2a28(r1)
 00017b3c: 8fbf0010 lw r31,0x0010(r29)
 00017b40: 27bd0018 addiu r29,r29,0x0018
 00017b44: 03e00008 jr r31
 00017b48: 00000000 nop
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