Difference between revisions of "Conditional Status Proc Roll (19%) Inner Routine"
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(Created page with "00187690: 3c028019 lui r2,0x8019 00187694: 8c42f5fc lw r2,-0x0a04(r2) 00187698: 27bdffe8 addiu r29,r29,0xffe8 0018769c: 1440000d bne r2,r0,0x001876d4 # if (mem_word[0x8018f...") |
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| − | 00187690: 3c028019 lui r2,0x8019 | + | 00187690: 3c028019 lui r2,0x8019 |
| − | 00187694: 8c42f5fc lw r2,-0x0a04(r2) | + | 00187694: 8c42f5fc lw r2,-0x0a04(r2) |
| − | 00187698: 27bdffe8 addiu r29,r29,0xffe8 | + | 00187698: 27bdffe8 addiu r29,r29,0xffe8 |
| − | 0018769c: 1440000d bne r2,r0,0x001876d4 | + | 0018769c: 1440000d bne r2,r0,0x001876d4 # if (mem_word[0x8018f5fc] != 0) |
| − | 001876a0: afbf0010 sw r31,0x0010(r29) # return; | + | 001876a0: afbf0010 sw r31,0x0010(r29) # return; |
| − | 001876a4: 34040064 ori r4,r0,0x0064 | + | 001876a4: 34040064 ori r4,r0,0x0064 |
| − | 001876a8: 0c017833 jal 0x0005e0cc # Random Roll (0-99) with Threshold = 19 (81% over/equal, 19% under) | + | 001876a8: 0c017833 jal 0x0005e0cc # Random Roll (0-99) with Threshold = 19 (81% over/equal, 19% under) |
| − | 001876ac: 34050013 ori r5,r0,0x0013 | + | 001876ac: 34050013 ori r5,r0,0x0013 |
| − | 001876b0: 14400008 bne r2,r0,0x001876d4 # if (Under) | + | 001876b0: 14400008 bne r2,r0,0x001876d4 # if (Under) |
| − | 001876b4: 00000000 nop # { | + | 001876b4: 00000000 nop # { |
| − | 001876b8: 3c038019 lui r3,0x8019 # | + | 001876b8: 3c038019 lui r3,0x8019 # |
| − | 001876bc: 8c632d90 lw r3,0x2d90(r3) | + | 001876bc: 8c632d90 lw r3,0x2d90(r3) |
| − | 001876c0: 00000000 nop | + | 001876c0: 00000000 nop |
| − | 001876c4: 94620010 lhu r2,0x0010(r3) | + | 001876c4: 94620010 lhu r2,0x0010(r3) |
| − | 001876c8: 00000000 nop | + | 001876c8: 00000000 nop |
| − | 001876cc: 34420200 ori r2,r2,0x0200 # (Set status proc to true)? -- *(&action + 0x11) |= 0x02; | + | 001876cc: 34420200 ori r2,r2,0x0200 # (Set status proc to true)? -- *(&action + 0x11) |= 0x02; |
| − | 001876d0: a4620010 sh r2,0x0010(r3) # } | + | 001876d0: a4620010 sh r2,0x0010(r3) # } |
| − | 001876d4: 8fbf0010 lw r31,0x0010(r29) | + | 001876d4: 8fbf0010 lw r31,0x0010(r29) |
| − | 001876d8: 27bd0018 addiu r29,r29,0x0018 | + | 001876d8: 27bd0018 addiu r29,r29,0x0018 |
| − | 001876dc: 03e00008 jr r31 # return; | + | 001876dc: 03e00008 jr r31 # return; |
| − | 001876e0: 00000000 nop | + | 001876e0: 00000000 nop |
Revision as of 02:44, 31 March 2012
00187690: 3c028019 lui r2,0x8019
00187694: 8c42f5fc lw r2,-0x0a04(r2)
00187698: 27bdffe8 addiu r29,r29,0xffe8
0018769c: 1440000d bne r2,r0,0x001876d4 # if (mem_word[0x8018f5fc] != 0)
001876a0: afbf0010 sw r31,0x0010(r29) # return;
001876a4: 34040064 ori r4,r0,0x0064
001876a8: 0c017833 jal 0x0005e0cc # Random Roll (0-99) with Threshold = 19 (81% over/equal, 19% under)
001876ac: 34050013 ori r5,r0,0x0013
001876b0: 14400008 bne r2,r0,0x001876d4 # if (Under)
001876b4: 00000000 nop # {
001876b8: 3c038019 lui r3,0x8019 #
001876bc: 8c632d90 lw r3,0x2d90(r3)
001876c0: 00000000 nop
001876c4: 94620010 lhu r2,0x0010(r3)
001876c8: 00000000 nop
001876cc: 34420200 ori r2,r2,0x0200 # (Set status proc to true)? -- *(&action + 0x11) |= 0x02;
001876d0: a4620010 sh r2,0x0010(r3) # }
001876d4: 8fbf0010 lw r31,0x0010(r29)
001876d8: 27bd0018 addiu r29,r29,0x0018
001876dc: 03e00008 jr r31 # return;
001876e0: 00000000 nop
