Difference between revisions of "Load Halfword"
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(Load Halfword) |
(Load Halfword: spacing) |
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| − | 00146078: 90830001 lbu r3,0x0001(r4) | + | 00146078: 90830001 lbu r3,0x0001(r4) |
| − | 0014607c: 90820000 lbu r2,0x0000(r4) | + | 0014607c: 90820000 lbu r2,0x0000(r4) |
| − | 00146080: 00031a00 sll r3,r3,0x08 | + | 00146080: 00031a00 sll r3,r3,0x08 |
| − | 00146084: 00431025 or r2,r2,r3 | + | 00146084: 00431025 or r2,r2,r3 |
| − | 00146088: 00021400 sll r2,r2,0x10 # Redundant? Upper 16 bits should already be zeroes by virtue of the two lbu commands. | + | 00146088: 00021400 sll r2,r2,0x10 # Redundant? Upper 16 bits should already be zeroes by virtue of the two lbu commands. |
| − | 0014608c: 03e00008 jr r31 | + | 0014608c: 03e00008 jr r31 |
| − | 00146090: 00021403 sra r2,r2,0x10 | + | 00146090: 00021403 sra r2,r2,0x10 |
Revision as of 23:26, 20 February 2013
00146078: 90830001 lbu r3,0x0001(r4) 0014607c: 90820000 lbu r2,0x0000(r4) 00146080: 00031a00 sll r3,r3,0x08 00146084: 00431025 or r2,r2,r3 00146088: 00021400 sll r2,r2,0x10 # Redundant? Upper 16 bits should already be zeroes by virtue of the two lbu commands. 0014608c: 03e00008 jr r31 00146090: 00021403 sra r2,r2,0x10
