Difference between revisions of "PSX instruction set"

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(Ported from http://xifanie.ffhacktics.com/zodiac/PSX-INST.txt with some minor corrections. --Raijinili)
 
(Warning about jalr argument order.)
 
(3 intermediate revisions by 2 users not shown)
Line 1: Line 1:
−
Mirror of [http://xifanie.ffhacktics.com/zodiac/PSX-INST.txt]
+
Mirror of [http://xifanie.ffhacktics.com/zodiac/PSX-INST.txt], with corrections.
 +
 
 +
'''Warning:''' Because [[psxfin]]'s disassembler uses the wrong order for [[jalr]], the FFH wiki and community uses "jalr rs,rd" instead of the correct "jalr rd,rs".
  
 
  Instruction    Description                                    Syntax          Result
 
  Instruction    Description                                    Syntax          Result
Line 10: Line 12:
 
  ANDI            And Immediate                  ANDI            rt, rs, immed.  rt = rs AND immed.
 
  ANDI            And Immediate                  ANDI            rt, rs, immed.  rt = rs AND immed.
 
  BEQ            Branch on Equal                BEQ            rs, rt, offset  if (rs = rt) branch
 
  BEQ            Branch on Equal                BEQ            rs, rt, offset  if (rs = rt) branch
−
BEQL            Branch on Equal Likely          BEQL            rs, rt, offset  if (rs = rt) branch(likely)
 
 
  BGEZ            Branch on >= 0                  BGEZ            rs, offset      if (rs > 0) branch
 
  BGEZ            Branch on >= 0                  BGEZ            rs, offset      if (rs > 0) branch
 
  BGEZAL          Branch >= 0 and Link            BGEZAL          rs, offset      if (rs >= 0) call/ret
 
  BGEZAL          Branch >= 0 and Link            BGEZAL          rs, offset      if (rs >= 0) call/ret
−
BGEZALL        Branch >= 0 and Link Likely    BGEZALL        rs, offset      if (rs >= 0) call/ret(likely)
 
−
BGEZL          Branch on >= 0 Likely          BGEZL          rs, offset      if (rs > 0) branch(likely)
 
 
  BGTZ            Branch > 0                      BGTZ            rs, offset      if (rs > 0) branch
 
  BGTZ            Branch > 0                      BGTZ            rs, offset      if (rs > 0) branch
−
BGTZL          Branch > 0 Likely              BGTZL          rs, offset      if (rs > 0) branch(likely)
 
 
  BLEZ            Branch <= 0                    BLEZ            rs, offset      if (rs <= 0) branch
 
  BLEZ            Branch <= 0                    BLEZ            rs, offset      if (rs <= 0) branch
−
BLEZL          Branch <= 0    Likely          BLEZL          rs, offset      if (rs <= 0) branch(likely)
 
 
  BLTZ            Branch < 0                      BLTZ            rs, offset      if (rs < 0) branch
 
  BLTZ            Branch < 0                      BLTZ            rs, offset      if (rs < 0) branch
 
  BLTZAL          Branch < 0 and Link            BLTZAL          rs, offset      if (rs < 0) call/return
 
  BLTZAL          Branch < 0 and Link            BLTZAL          rs, offset      if (rs < 0) call/return
−
BLTZALL        Branch < 0 and Link Likely      BLTZALL        rs, offset      if (rs < 0) call/ret-likely
 
−
BLTZL          Branch < 0 Likely              BLTZL          rs, offset      if (rs < 0) branch(likely)
 
 
  BNE            Branch !=                      BNE            rs, rt, offset  if (rs != rt) branch
 
  BNE            Branch !=                      BNE            rs, rt, offset  if (rs != rt) branch
−
BNEL            Branch != Likely                BNEL            rs, rt, offset  if (rs != rt) branch(likely)
 
 
  BREAK          Breakpoint                      BREAK                          breakpoint exception
 
  BREAK          Breakpoint                      BREAK                          breakpoint exception
 
  COPz            Coprocessor Operation          COP(0/1/2/3)    function        copressor operation
 
  COPz            Coprocessor Operation          COP(0/1/2/3)    function        copressor operation
−
DADD            Doubleword Add                  DADD            rd, rs, rt      rd = rs + rt
 
−
DADDI          Doubleword Add Immediate        DADD            rd, rs, immed.  rd = rs + immed.
 
−
DADDIU          Doubleword Add Immed Unsigned  DADDIU          rd, rs, immed.  rd = rs + immed.
 
−
DADDU          Doubleword Add Unsigned        DADDU          rd, rs, rt      rd = rs + rt
 
−
DDIV            Doubleword Divide              DDIV            rs, rt          LO = rs / rt | HI = rs % rt 1
 
−
DDIVU          Doubleword Divide Unsigned      DDIVU          rs, rt          LO = rs / rt | HI = rs % rt 1
 
 
  DIV            Divide Word                    DIV            rs, rt          LO = rs / rt | HI = rs % rt 1
 
  DIV            Divide Word                    DIV            rs, rt          LO = rs / rt | HI = rs % rt 1
 
  DIVU            Divide Word    Unsigned        DIVU            rs, rt          LO = rs / rt | HI = rs % rt 1
 
  DIVU            Divide Word    Unsigned        DIVU            rs, rt          LO = rs / rt | HI = rs % rt 1
−
DMULT          Doubleword Multiply            DMULT          rs, rt          LO = rs * rt | HI = rs * rt 2
 
−
DMULTU          Doubleword Multiply Unsigned    DMULTU          rs, rt          LO = rs * rt | HI = rs * rt 2
 
−
DSLL            Doubleword Shift Left Logical  DSLL            rd, rt, sa      rd = rt << sa              3
 
−
DSLL32          Doubleword << Logic +32        DSLL32          rd, rt, sa      rd = rt << (sa + 32)        3
 
−
DSLLV          Doubleword << Logic. Variable  DSLLV          rd, rt, rs      rd = rt << rs              3
 
−
DSRA            Doubleword << Arithmetic        DSRA            rd, rt, sa      rd = rt >> sa              4
 
−
DSRA32          Doubleword << Arith +32        DSRA32          rd, rt, sa      rd = rt >> (sa + 32)        4
 
−
DSRAV          Doubleword >> Arith Variable    DSRAV          rd, rt, rs      rd = rt >> rs              4
 
−
DSRL            Doubleword Shift Right Logic.  DSRL            rd, rt, sa      rd = rt >> sa              3
 
−
DSRL32          Doubleword >> Logic+32          DSRL32          rd, rt, sa      rd = rt >> (sa + 32)        3
 
−
DSRLV          Doubleword >> Logic. Variable  DSRLV          rd, rt, rs      rd = rt >> rs              3
 
−
DSUB            Doubleword Subtract            DSUB            rd, rs, rt      rd = rs - rt
 
−
DSUBU          Doubleword Subtract Unsigned    DSUBU          rd, rs, rt      rd = rs - rt
 
 
  J              Jump                            J              address        jumps within 256MB
 
  J              Jump                            J              address        jumps within 256MB
 
  JAL            Jump and Link                  JAL            address        jumps within 256MB, and ret
 
  JAL            Jump and Link                  JAL            address        jumps within 256MB, and ret
Line 55: Line 30:
 
  LB              Load Byte                      LB              rt, off(base)  rt = memory[base+off] 8 bit
 
  LB              Load Byte                      LB              rt, off(base)  rt = memory[base+off] 8 bit
 
  LBU            Load Byte Unsigned              LBU            rt, off(base)  rt = memory[base+off] 8 bit
 
  LBU            Load Byte Unsigned              LBU            rt, off(base)  rt = memory[base+off] 8 bit
−
LD              Load Doubleword                LD              rt, off(base)  rt = memory[base+off] 64 bit
 
−
LDCz            Load Doubleword to Coprocess    LDC(1/2)        rt, off(base)  rt = memory[base+off] 64 bit
 
−
LDL            Load Doubleword Left            LDL            rt, off(base)  rt = memory[base+off]      6
 
−
LDR            Load Doubleword Right          LDR            rt, off(base)  rt = memory[base+off]      6
 
 
  LH              Load Halfword                  LH              rt, off(base)  rt = memory[base+off] 16 bit
 
  LH              Load Halfword                  LH              rt, off(base)  rt = memory[base+off] 16 bit
 
  LHU            Load Halfword Unsigned          LHU            rt, off(base)  rt = memory[base+off] 16 bit
 
  LHU            Load Halfword Unsigned          LHU            rt, off(base)  rt = memory[base+off] 16 bit
−
LL              Load Linked Word                LL              rt, off(base)  rt = memory[base+off]
 
−
LLD            Load Linked Doubleword          LLD            rt, off(base)  rt = memory[base+off]
 
 
  LUI            Load Upper Immediate            LUI            rt, immed.      rt = immed. << 16
 
  LUI            Load Upper Immediate            LUI            rt, immed.      rt = immed. << 16
 
  LW              Load Word                      LW              rt, offset(base)rt = memory[base+off] 32 bit
 
  LW              Load Word                      LW              rt, offset(base)rt = memory[base+off] 32 bit
Line 68: Line 37:
 
  LWL            Load Word Left                  LWL            rt, offset(base)rt = memory[base+off]      6
 
  LWL            Load Word Left                  LWL            rt, offset(base)rt = memory[base+off]      6
 
  LWR            Load Word Right                LWR            rt, offset(base)rt = memory[base+off]      6
 
  LWR            Load Word Right                LWR            rt, offset(base)rt = memory[base+off]      6
−
LWU            Load Word Unsigned              LWU            rt, offset(base)rt = memory[base+off] 32 bit
 
 
  MFHI            Move From HI Register          MFHI            rd              rd = HI
 
  MFHI            Move From HI Register          MFHI            rd              rd = HI
 
  MFLO            Move From LO Register          MFLO            rd              rd = LO
 
  MFLO            Move From LO Register          MFLO            rd              rd = LO
−
MOVN            Move Conditional on Not Zero    MOVN            rd, rs, rt      if (rt != 0) rd = rs
 
−
MOVZ            Move Conditional on Zero        MOVZ            rd, rs, rt      if (rt = 0) rd = rs
 
 
  MTHI            Move To HI Register            MTHI            rd              HI = rd
 
  MTHI            Move To HI Register            MTHI            rd              HI = rd
 
  MTLO            Move To LO Register            MTLO            rd              LO = rd
 
  MTLO            Move To LO Register            MTLO            rd              LO = rd
Line 80: Line 46:
 
  OR              Or                              OR              rd, rs, rt      rd = rs OR rt
 
  OR              Or                              OR              rd, rs, rt      rd = rs OR rt
 
  ORI            Or Immediate                    ORI            rd, rs, immed.  rd = rs OR immed
 
  ORI            Or Immediate                    ORI            rd, rs, immed.  rd = rs OR immed
−
PREF            Prefetch                        PREF            type, off(base) See prefetch table for type
 
 
  SB              Store Byte                      SB              rt, off(base)  memory[base+off] = rt 8 bit
 
  SB              Store Byte                      SB              rt, off(base)  memory[base+off] = rt 8 bit
−
SC              Store Conditional Word          SC              rt, off(base)  memory[base+off] = rt 8 bit 7
 
−
SCD            Store Conditional Doubleword    SCD            rt, off(base)  memory[base+off] = rt 64 bit7
 
−
SD              Store Doubleword                SD              rt, off(base)  memory[base+off] = rt 64 bit
 
−
SDCz            Store Doubleword From Copr      SDC(1/2)        rt, off(base)  memory[base+off] = rt 64 bit
 
−
SDL            Store Doubleword Left          SDL            rt, off(base)  memory[base+off] = rt 64 bit8
 
−
SDR            Store Doubleword Right          SDR            rt, off(base)  memory[base+off] = rt 64 bit8
 
 
  SH              Store Halfword                  SH              rt, off(base)  memory[base+off] = rt 16 bit
 
  SH              Store Halfword                  SH              rt, off(base)  memory[base+off] = rt 16 bit
 
  SLL            Shift Word Left Logical        SLL            rd, rt, sa      rd = rt << sa              3
 
  SLL            Shift Word Left Logical        SLL            rd, rt, sa      rd = rt << sa              3
Line 94: Line 53:
 
  SLTI            Set On Less Than Immediate      SLTI            rd, rs, immed.  rd = (rs < immed)
 
  SLTI            Set On Less Than Immediate      SLTI            rd, rs, immed.  rd = (rs < immed)
 
  SLTIU          Set On < Immediate Unsigned    SLTIU          rd, rs, immed.  rd = (rs < immed)
 
  SLTIU          Set On < Immediate Unsigned    SLTIU          rd, rs, immed.  rd = (rs < immed)
−
  SLT            Set On Less Than Unsigned      SLTU            rd, rs, rt      rd = (rs < rt)
+
  SLTU            Set On Less Than Unsigned      SLTU            rd, rs, rt      rd = (rs < rt)
 
  SRA            Shift Word Right Arithmetic    SRA            rd, rt, sa      rd = rt >> sa              4
 
  SRA            Shift Word Right Arithmetic    SRA            rd, rt, sa      rd = rt >> sa              4
 
  SRAV            Shift Word >> Arith Variable    SRAV            rd, rt, rs      rd = rt >> rs              4
 
  SRAV            Shift Word >> Arith Variable    SRAV            rd, rt, rs      rd = rt >> rs              4
Line 105: Line 64:
 
  SWL            Store Word Left                SWL            rt, off (base)  memory[base+off] = rt 32 bit8
 
  SWL            Store Word Left                SWL            rt, off (base)  memory[base+off] = rt 32 bit8
 
  SWR            Store Word Right                SWR            rt, off (base)  memory[base+off] = rt 32 bit8
 
  SWR            Store Word Right                SWR            rt, off (base)  memory[base+off] = rt 32 bit8
−
SYNC            Synchronize Shared Memory      SYNC                            Synchronizes memory
 
 
  SYSCALL        System Call                    SYSCALL                        Causes System Call exception
 
  SYSCALL        System Call                    SYSCALL                        Causes System Call exception
−
TEQ            Trap if Equal                  TEQ            rs, rt          if (rs = rt) Trap
 
−
TEQI            Trap if Equal Immediate        TEQI            rs, immed.      if (rs = immed) Trap
 
−
TGE            Trap if Greater or Equal        TGE            rs, rt          if (rs >= rt) Trap
 
−
TGEI            Trap if >= Immediate            TGEI            rs, immed      if (rs >= immed) Trap
 
−
TGEIU          Trap if >= Immediate Unsigned  TGEIU          rs, immed      if (rs >= immed) Trap
 
−
TGEU            Trap if >= Unsigned            TGEU            rs, rt          if (rs >= rt) Trap
 
−
TLT            Trap if Less Than              TLT            rs, rt          if (rs < rt) Trap
 
−
TLTI            Trap if Less Than Immediate    TLTI            rs, immed      if (rs < immed) Trap
 
−
TLTIU          Trap if < Immediate Unsigned    TLTIU          rs, immed      if (rs < immed) Trap
 
−
TLTU            Trap if Less Than Unsigned      TLT            rs, rt          if (rs < rt) Trap
 
−
TNE            Trap if Not Equal              TNE            rs, rt          if (rs != rt) Trap
 
−
TNEI            Trap if Not Equal Immediate    TNEI            rs, immed.      if (rs != immed) Trap
 
 
  XOR            Exclusive Or                    XOR            rd, rs, rt      rd = rs XOR rt
 
  XOR            Exclusive Or                    XOR            rd, rs, rt      rd = rs XOR rt
 
  XORI            Exclusive Or Immediate          XORI            rt, rs, immed  rt = rs XOR immed
 
  XORI            Exclusive Or Immediate          XORI            rt, rs, immed  rt = rs XOR immed
 
   
 
   
 
  Notes:
 
  Notes:
−
  1.      LOW holds the integer value of the divide, HI holds the remainder.
+
  1.      LO holds the integer value of the divide, HI holds the remainder.
−
  2.      LOW holds the low 32 bits of the multiply, HI holds the high 32 bits of the multiply.
+
  2.      LO holds the low 32 bits of the multiply, HI holds the high 32 bits of the multiply.
−
  3.      On logical shifts 0s are inserted in the incoming bits.
+
  3.      On logical shifts, 0s are inserted in the incoming bits.
−
  4.      On arithmetic shifts the sign bit is duplicated in the incoming bits.
+
  4.      On arithmetic shifts, the sign bit is duplicated in the incoming bits.
 
  5.      JALR instructions jumps to GPR(rs), and uses rd to select GPR for return. Defaults to 31.
 
  5.      JALR instructions jumps to GPR(rs), and uses rd to select GPR for return. Defaults to 31.
−
  6.      LDL, LDR, LWL, and LWR load parts of a double word from unaligned memory
+
  6.      LWL and LWR load parts of a word from unaligned memory
−
7.      SC, SCD only updates if changes were made?
 
−
8.      SDL, SDR, SWL, and SWR store parts of a double word to unaligned memory
 
−
Prefetch Table
 
 
   
 
   
−
  Value  Name            Description
+
  8.      SWL and SWR store parts of a word to unaligned memory
−
-----  ----            -----------
 
−
0      load            Data is expected to be loaded but not modified
 
−
1      store           Data is expected to be stored or modified
 
−
2-3    -----          Not defined
 
−
4      load_streamed  Data is expected to be loaded but not reused, and not modified
 
−
5      store_streamed  Data is expected to be stored or modified, but not reused
 
−
6      load_retained  Data is expected to be loaded and reused, but not modified
 
−
7      store_retained  Data is expected to be stored or modified, and reused
 
−
8-31    -----          Not defined
 

Latest revision as of 06:25, 20 August 2019

Mirror of [1], with corrections.

Warning: Because psxfin's disassembler uses the wrong order for jalr, the FFH wiki and community uses "jalr rs,rd" instead of the correct "jalr rd,rs". 

Instruction     Description                                     Syntax          Result
-----------     -----------                                     ------          ------
ADD             Add Word                        ADD             rd, rs, rt      rd = rs + rt
ADDI            Add Immediate Word              ADDI            rt, rs, immed   rt = rs + immed.
ADDIU           Add Immediate Unsigned Word     ADDIU           rt, rs, immed.  rt = rs + immed.
ADDU            Add Unsigned Word               ADDU            rd, rs, rt      rd = rs + rt
AND             And                             AND             rd, rs, rt      rd = rs AND rt
ANDI            And Immediate                   ANDI            rt, rs, immed.  rt = rs AND immed.
BEQ             Branch on Equal                 BEQ             rs, rt, offset  if (rs = rt) branch
BGEZ            Branch on >= 0                  BGEZ            rs, offset      if (rs > 0) branch
BGEZAL          Branch >= 0 and Link            BGEZAL          rs, offset      if (rs >= 0) call/ret
BGTZ            Branch > 0                      BGTZ            rs, offset      if (rs > 0) branch
BLEZ            Branch <= 0                     BLEZ            rs, offset      if (rs <= 0) branch
BLTZ            Branch < 0                      BLTZ            rs, offset      if (rs < 0) branch
BLTZAL          Branch < 0 and Link             BLTZAL          rs, offset      if (rs < 0) call/return
BNE             Branch !=                       BNE             rs, rt, offset  if (rs != rt) branch
BREAK           Breakpoint                      BREAK                           breakpoint exception
COPz            Coprocessor Operation           COP(0/1/2/3)    function        copressor operation
DIV             Divide Word                     DIV             rs, rt          LO = rs / rt | HI = rs % rt 1
DIVU            Divide Word     Unsigned        DIVU            rs, rt          LO = rs / rt | HI = rs % rt 1
J               Jump                            J               address         jumps within 256MB
JAL             Jump and Link                   JAL             address         jumps within 256MB, and ret
JALR            Jump and Link Register          JALR            rs (rd = 31)    jumps within 256MB, and ret 5
----                                            JALR            rd, rs                                      5
JR              Jump Register                   JR              rs              jumps to GPR(rs)
LB              Load Byte                       LB              rt, off(base)   rt = memory[base+off] 8 bit
LBU             Load Byte Unsigned              LBU             rt, off(base)   rt = memory[base+off] 8 bit
LH              Load Halfword                   LH              rt, off(base)   rt = memory[base+off] 16 bit
LHU             Load Halfword Unsigned          LHU             rt, off(base)   rt = memory[base+off] 16 bit
LUI             Load Upper Immediate            LUI             rt, immed.      rt = immed. << 16
LW              Load Word                       LW              rt, offset(base)rt = memory[base+off] 32 bit
LWCz            Load Word to Coprocessor        LWC(1/2/3)      rt, offs(base)  rt = memory[base+off] 32 bit
LWL             Load Word Left                  LWL             rt, offset(base)rt = memory[base+off]       6
LWR             Load Word Right                 LWR             rt, offset(base)rt = memory[base+off]       6
MFHI            Move From HI Register           MFHI            rd              rd = HI
MFLO            Move From LO Register           MFLO            rd              rd = LO
MTHI            Move To HI Register             MTHI            rd              HI = rd
MTLO            Move To LO Register             MTLO            rd              LO = rd
MULT            Multiply Word                   MULT            rs, rt          LO = rs * rt | HI = rs * rt 2
MULTU           Multiply Unsigned Word          MULTU           rs, rt          LO = rs * rt | HI = rs * rt 2
NOR             Not Or                          NOR             rd, rs, rt      rd = rs NOR rt
OR              Or                              OR              rd, rs, rt      rd = rs OR rt
ORI             Or Immediate                    ORI             rd, rs, immed.  rd = rs OR immed
SB              Store Byte                      SB              rt, off(base)   memory[base+off] = rt 8 bit
SH              Store Halfword                  SH              rt, off(base)   memory[base+off] = rt 16 bit
SLL             Shift Word Left Logical         SLL             rd, rt, sa      rd = rt << sa               3
SLLV            Shift Word Left Logic Variab    SLLV            rd, rt, rs      rd = rt << rs               3
SLT             Set On Less Than                SLT             rd, rs, rt      rd = (rs < rt)
SLTI            Set On Less Than Immediate      SLTI            rd, rs, immed.  rd = (rs < immed)
SLTIU           Set On < Immediate Unsigned     SLTIU           rd, rs, immed.  rd = (rs < immed)
SLTU            Set On Less Than Unsigned       SLTU            rd, rs, rt      rd = (rs < rt)
SRA             Shift Word Right Arithmetic     SRA             rd, rt, sa      rd = rt >> sa               4
SRAV            Shift Word >> Arith Variable    SRAV            rd, rt, rs      rd = rt >> rs               4
SRL             Shift Word Right Logical        SRL             rd, rt, sa      rd = rt >> sa               3
SRLV            Shift Word Right Logic Variab   SRLV            rd, rt, rs      rd = rt >> rs               3
SUB             Subtract Word                   SUB             rd, rs, rt      rd = rs - rt
SUBU            Subtract Unsigned Word          SUBU            rd, rs, rt      rd = rs - rt
SW              Store Word                      SW              rt, off(base)   memory[base+off] = rt 32 bit
SWCz            Store Word From Coprocessor     SWC(1/2/3)      rt, off(base)   memory[base+off] = rt 32 bit
SWL             Store Word Left                 SWL             rt, off (base)  memory[base+off] = rt 32 bit8
SWR             Store Word Right                SWR             rt, off (base)  memory[base+off] = rt 32 bit8
SYSCALL         System Call                     SYSCALL                         Causes System Call exception
XOR             Exclusive Or                    XOR             rd, rs, rt      rd = rs XOR rt
XORI            Exclusive Or Immediate          XORI            rt, rs, immed   rt = rs XOR immed

Notes:
1.      LO holds the integer value of the divide, HI holds the remainder.
2.      LO holds the low 32 bits of the multiply, HI holds the high 32 bits of the multiply.
3.      On logical shifts, 0s are inserted in the incoming bits.
4.      On arithmetic shifts, the sign bit is duplicated in the incoming bits.
5.      JALR instructions jumps to GPR(rs), and uses rd to select GPR for return. Defaults to 31.
6.      LWL and LWR load parts of a word from unaligned memory

8.      SWL and SWR store parts of a word to unaligned memory
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