E004 001c2500 - 001c39f4

001c2500: addiu r29,r29,-0x0680
001c2504: sw r30,0x0678(r29)
001c2508: sll r4,r4,0x10
001c250c: sw r16,0x0658(r29)
001c2510: sra r16,r4,0x10                  phase (?)
001c2514: sll r2,r16,0x05                  p1 * 0x20
001c2518: subu r2,r2,r16                   p1 * 0x1f
001c251c: sw r18,0x0660(r29)
001c2520: sll r18,r2,0x03                  p1 * 0xf8
001c2524: lui r2,0x801c
001c2528: addiu r2,r2,-0x0fd4              temp effect data
001c252c: sw r23,0x0674(r29)
001c2530: addu r23,r18,r2                  temp effect data for current phase
001c2534: sll r2,r6,0x01                   p3 * 2
001c2538: addu r2,r2,r6                    p3 * 3
001c253c: sll r2,r2,0x04                   p3 * 0x30
001c2540: addu r2,r2,r6                    p3 * 0x31
001c2544: sll r2,r2,0x02                   p3 * 0xc4
001c2548: lui r3,0x801c
001c254c: lw r3,-0x4078(r3)                pointer to raw model data in effect file
001c2550: addiu r2,r2,0x0014               p3 * 0xc4 + 0x14
001c2554: sw r31,0x067c(r29)
001c2558: sw r22,0x0670(r29)
001c255c: sw r21,0x066c(r29)
001c2560: sw r20,0x0668(r29)
001c2564: sw r19,0x0664(r29)
001c2568: sw r17,0x065c(r29)
001c256c: sw r7,0x05f8(r29)                 holy shit. anyway, stores p4 to 0x05f8 stack
001c2570: addu r19,r2,r3                    effect model data pointer
001c2574: lhu r20,0x0002(r19)
001c2578: jal 0x00044a60                    Find Address for Polygons by Depth <- get Otag list
001c257c: addu r30,r5,r0                    p2
001c2580: addu r17,r23,r30                  temp effect data + p2
001c2584: sw r2,0x0620(r29)
001c2588: lbu r3,0x0022(r17)                current model executing phase
001c258c: ori r4,r0,0x0001
001c2590: beq r3,r4,0x001c25bc              go here if initialising
001c2594: slti r2,r3,0x0002
001c2598: bne r2,r0,0x001c39c4              go here if erroneous
001c259c: nop
001c25a0: ori r2,r0,0x0002
001c25a4: beq r3,r2,0x001c2694              go here if executing
001c25a8: ori r2,r0,0x0003
001c25ac: beq r3,r2,0x001c3984              go here if ending
001c25b0: nop
001c25b4: j 0x001c39c4                      erroneous
001c25b8: nop

0x22 TED == 1 (initialise model)

001c25bc: sll r2,r30,0x02
001c25c0: addu r17,r2,r23
001c25c4: lw r4,0x00e4(r17)
001c25c8: nop
001c25cc: beq r4,r0,0x001c25dc
001c25d0: addu r18,r0,r0
001c25d4: jal 0x001a4e9c
001c25d8: nop
001c25dc: ori r4,r0,0x1a1c
001c25e0: jal 0x001a4de8                        0x1a4de8 <-- locate file native model data
001c25e4: addu r5,r16,r0
001c25e8: addu r22,r2,r0
001c25ec: sw r22,0x00e4(r17)                    store pointer to model data
001c25f0: lhu r3,0x0024(r19)                    effect wide polygon data?
001c25f4: ori r19,r0,0x0004
001c25f8: andi r2,r3,0x0003
001c25fc: sll r2,r2,0x05
001c2600: ori r21,r2,0x0086
001c2604: andi r3,r3,0x0004                     transparent check
001c2608: sltiu r20,r3,0x0001                   1 if not transparent.
001c260c: addu r17,r0,r0
001c2610: addu r16,r22,r19

001c2614: jal 0x00023d44                        P19 SetPolyGT4
001c2618: addu r4,r16,r0
001c261c: beq r20,r0,0x001c2630                 if r20 = 0, set transparency to true
001c2620: nop
001c2624: lbu r2,0x0007(r16)                    load poly type
001c2628: j 0x001c263c
001c262c: ori r2,r2,0x0002                      enable transparency
001c2630: lbu r2,0x0007(r16)
001c2634: nop
001c2638: andi r2,r2,0x00fd                     disable transparency
001c263c: sb r2,0x0007(r16)                     store with/without transparency
001c2640: ori r2,r0,0x7b00
001c2644: sh r21,0x001a(r16)                    always maps v2u2 to a certain position...?
001c2648: sh r2,0x000e(r16)                     set CLUT to 0x7b00
001c264c: addiu r17,r17,0x0001
001c2650: slti r2,r17,0x0040
001c2654: bne r2,r0,0x001c2614                  loop 0x40 times
001c2658: addiu r16,r16,0x0034

001c265c: addiu r18,r18,0x0001
001c2660: slti r2,r18,0x0002                    do twice (0x80 polygons)
001c2664: bne r2,r0,0x001c260c
001c2668: addiu r19,r19,0x0d00                  to next?
001c266c: addu r3,r23,r30                       p1 & p2 diff?

001c2670: ori r2,r0,0x0002
001c2674: sh r0,0x1a04(r22)
001c2678: sh r0,0x1a06(r22)
001c267c: sw r0,0x0000(r22)
001c2680: sw r0,0x1a08(r22)
001c2684: sw r0,0x1a0c(r22)
001c2688: sw r0,0x1a18(r22)
001c268c: j 0x001c39c4
001c2690: sb r2,0x0022(r3)                      update model phase to execute

if 0x22 TED == 2 (execute)

001c2694: sll r2,r30,0x02                       p2 * 4
001c2698: addu r2,r2,r23                        temp effect data + p2 * 4?
001c269c: lw r22,0x00e4(r2)                     current model pointer
001c26a0: addiu r2,r0,-0x0001
001c26a4: lw r3,0x0008(r19)
001c26a8: lui r1,0x801c
001c26ac: addu r1,r1,r18
001c26b0: lbu r16,-0x0fae(r1)                   0x801bf052, 0x30 something
001c26b4: andi r17,r3,0x000f
001c26b8: addiu r17,r17,-0x0001
001c26bc: beq r17,r2,0x001c26ec                 if == 0, clears phase index multiple thing,
001c26c0: sll r2,r17,0x02
001c26c4: addu r2,r2,r17
001c26c8: sll r2,r2,0x05
001c26cc: lui r3,0x801c
001c26d0: lw r3,-0x4084(r3)
001c26d4: lw r25,0x05f8(r29)                    p4
001c26d8: addu r2,r2,r3
001c26dc: addu r2,r2,r25
001c26e0: lbu r18,0x0004(r2)
001c26e4: j 0x001c26f4
001c26e8: addu r4,r19,r0

001c26ec: addu r18,r0,r0
001c26f0: addu r4,r19,r0                         has raw effect model data
001c26f4: addu r5,r18,r0                         transform value? just. 0
001c26f8: jal 0x001a8c14                         fetch effect model data? returned into r6 pointer. 
001c26fc: addiu r6,r29,0x05b0                    parse stack + 0x5b0?
001c2700: andi r3,r20,0x0e00
001c2704: ori r2,r0,0x0400
001c2708: beq r3,r2,0x001c27f0
001c270c: slti r2,r3,0x0401
001c2710: beq r2,r0,0x001c2730
001c2714: nop
001c2718: beq r3,r0,0x001c2888
001c271c: ori r2,r0,0x0200
001c2720: beq r3,r2,0x001c2768
001c2724: nop
001c2728: j 0x001c2888
001c272c: nop

001c2730: ori r2,r0,0x0800
001c2734: beq r3,r2,0x001c2888
001c2738: slti r2,r3,0x0801
001c273c: beq r2,r0,0x001c2754
001c2740: ori r2,r0,0x0600
001c2744: beq r3,r2,0x001c27f4
001c2748: addu r5,r16,r0
001c274c: j 0x001c2888
001c2750: nop

001c2754: ori r2,r0,0x0a00
001c2758: beq r3,r2,0x001c2848
001c275c: nop
001c2760: j 0x001c2888
001c2764: nop

001c2768: lui r16,0x801c
001c276c: addiu r16,r16,-0x5236
001c2770: lh r4,0x0000(r16)
001c2774: lui r5,0x801c
001c2778: lh r5,-0x5232(r5)
001c277c: lui r6,0x801c
001c2780: lh r6,-0x5234(r6)
001c2784: jal 0x00183fb4
001c2788: nop
001c278c: lw r4,0x05b0(r29)
001c2790: lh r5,0x0000(r16)
001c2794: addiu r4,r4,0x000e
001c2798: sll r3,r5,0x03
001c279c: subu r3,r3,r5
001c27a0: sll r3,r3,0x02
001c27a4: addu r4,r4,r3
001c27a8: sw r4,0x05b0(r29)
001c27ac: lw r4,0x05b8(r29)
001c27b0: lui r5,0x801c
001c27b4: lh r5,-0x5232(r5)
001c27b8: addiu r4,r4,0x000e
001c27bc: sll r3,r5,0x03
001c27c0: subu r3,r3,r5
001c27c4: sll r3,r3,0x02
001c27c8: addu r4,r4,r3
001c27cc: lbu r5,0x0002(r2)
001c27d0: lw r3,0x05b4(r29)
001c27d4: sw r4,0x05b8(r29)
001c27d8: sll r2,r5,0x01
001c27dc: addu r2,r2,r5
001c27e0: sll r2,r2,0x02
001c27e4: subu r3,r3,r2
001c27e8: j 0x001c2888
001c27ec: sw r3,0x05b4(r29)
001c27f0: addiu r5,r0,-0x0001
001c27f4: lui r2,0x801c
001c27f8: lw r2,-0x5338(r2)
001c27fc: lui r6,0x801c
001c2800: addiu r6,r6,-0x52f4
001c2804: lw r4,0x0000(r2)
001c2808: addiu r7,r29,0x0010
001c280c: jal 0x001a90d0
001c2810: andi r4,r4,0x0008
001c2814: lh r2,0x0010(r29)
001c2818: lw r3,0x05b0(r29)
001c281c: lw r4,0x05b4(r29)
001c2820: lw r5,0x05b8(r29)
001c2824: addu r2,r2,r3
001c2828: sw r2,0x05b0(r29)
001c282c: lh r2,0x0012(r29)
001c2830: lh r3,0x0014(r29)
001c2834: addu r2,r2,r4
001c2838: addu r3,r3,r5
001c283c: sw r2,0x05b4(r29)
001c2840: j 0x001c2888
001c2844: sw r3,0x05b8(r29)

001c2848: jal 0x0008df48
001c284c: addiu r4,r29,0x05f0
001c2850: lh r3,0x05f0(r29)
001c2854: lh r4,0x05f4(r29)
001c2858: sll r2,r3,0x03
001c285c: subu r2,r2,r3
001c2860: lw r3,0x05b0(r29)
001c2864: sll r2,r2,0x01
001c2868: addu r2,r2,r3
001c286c: sw r2,0x05b0(r29)
001c2870: sll r2,r4,0x03
001c2874: subu r2,r2,r4
001c2878: lw r3,0x05b8(r29)
001c287c: sll r2,r2,0x01
001c2880: addu r2,r2,r3
001c2884: sw r2,0x05b8(r29)
001c2888: lhu r2,0x000e(r19)
001c288c: nop
001c2890: andi r17,r2,0x000f
001c2894: addiu r17,r17,-0x0001
001c2898: addiu r2,r0,-0x0001
001c289c: beq r17,r2,0x001c28cc
001c28a0: sll r2,r17,0x02
001c28a4: addu r2,r2,r17
001c28a8: sll r2,r2,0x05
001c28ac: lui r3,0x801c
001c28b0: lw r3,-0x4084(r3)
001c28b4: lw r24,0x05f8(r29)
001c28b8: addu r2,r2,r3
001c28bc: addu r2,r2,r24
001c28c0: lbu r18,0x0004(r2)
001c28c4: j 0x001c28d0
001c28c8: nop

001c28cc: addu r18,r0,r0
001c28d0: lh r4,0x00a8(r19)
001c28d4: lh r5,0x00ac(r19)
001c28d8: jal 0x001a8be0
001c28dc: addu r6,r18,r0
001c28e0: addu r16,r2,r0
001c28e4: lw r3,0x0008(r19)
001c28e8: addiu r2,r0,-0x0001
001c28ec: srl r3,r3,0x08
001c28f0: andi r17,r3,0x000f
001c28f4: addiu r17,r17,-0x0001
001c28f8: beq r17,r2,0x001c2928
001c28fc: sll r2,r17,0x02
001c2900: addu r2,r2,r17
001c2904: sll r2,r2,0x05
001c2908: lui r3,0x801c
001c290c: lw r3,-0x4084(r3)
001c2910: lw r25,0x05f8(r29)
001c2914: addu r2,r2,r3
001c2918: addu r2,r2,r25
001c291c: lbu r18,0x0004(r2)
001c2920: j 0x001c292c
001c2924: nop

001c2928: addu r18,r0,r0
001c292c: lh r4,0x002c(r19)
001c2930: lh r5,0x0032(r19)
001c2934: jal 0x001a8be0
001c2938: addu r6,r18,r0
001c293c: lh r4,0x002e(r19)
001c2940: lh r5,0x0034(r19)
001c2944: addu r6,r18,r0
001c2948: jal 0x001a8be0
001c294c: sw r2,0x0600(r29)
001c2950: lh r24,0x0020(r19)
001c2954: nop
001c2958: sw r24,0x0610(r29)
001c295c: lhu r4,0x1a06(r22)
001c2960: lhu r3,0x0030(r19)
001c2964: lh r25,0x0022(r19)                     load model phase
001c2968: addu r4,r4,r3
001c296c: sw r25,0x0618(r29)                     store model phase
001c2970: sh r4,0x1a06(r22)
001c2974: sw r2,0x0608(r29)
001c2978: sll r2,r4,0x10
001c297c: sra r2,r2,0x10
001c2980: sll r5,r25,0x08
001c2984: slt r2,r5,r2
001c2988: beq r2,r0,0x001c2994
001c298c: subu r2,r4,r5
001c2990: sh r2,0x1a06(r22)
001c2994: lh r2,0x1a06(r22)
001c2998: nop
001c299c: bgez r2,0x001c29ac
001c29a0: addu r3,r2,r0
001c29a4: addu r2,r3,r5
001c29a8: sh r2,0x1a06(r22)
001c29ac: lw r2,0x000c(r19)
001c29b0: nop
001c29b4: andi r17,r2,0x000f
001c29b8: addiu r17,r17,-0x0001
001c29bc: addiu r2,r0,-0x0001
001c29c0: beq r17,r2,0x001c29f0
001c29c4: sll r2,r17,0x02
001c29c8: addu r2,r2,r17
001c29cc: sll r2,r2,0x05
001c29d0: lui r3,0x801c
001c29d4: lw r3,-0x4084(r3)
001c29d8: lw r24,0x05f8(r29)
001c29dc: addu r2,r2,r3
001c29e0: addu r2,r2,r24
001c29e4: lbu r18,0x0004(r2)
001c29e8: j 0x001c29f4
001c29ec: nop

001c29f0: addu r18,r0,r0
001c29f4: lh r4,0x0064(r19)
001c29f8: lh r5,0x0070(r19)
001c29fc: jal 0x001a8be0
001c2a00: addu r6,r18,r0
001c2a04: sw r2,0x0030(r29)
001c2a08: lh r4,0x0068(r19)
001c2a0c: lh r5,0x0074(r19)
001c2a10: jal 0x001a8be0
001c2a14: addu r6,r18,r0
001c2a18: sw r2,0x0034(r29)
001c2a1c: lh r4,0x006c(r19)
001c2a20: lh r5,0x0078(r19)
001c2a24: jal 0x001a8be0
001c2a28: addu r6,r18,r0
001c2a2c: sw r2,0x0038(r29)
001c2a30: lw r2,0x000c(r19)
001c2a34: nop
001c2a38: srl r2,r2,0x04
001c2a3c: andi r17,r2,0x000f
001c2a40: addiu r17,r17,-0x0001
001c2a44: addiu r2,r0,-0x0001
001c2a48: beq r17,r2,0x001c2a78
001c2a4c: sll r2,r17,0x02
001c2a50: addu r2,r2,r17
001c2a54: sll r2,r2,0x05
001c2a58: lui r3,0x801c
001c2a5c: lw r3,-0x4084(r3)
001c2a60: lw r25,0x05f8(r29)
001c2a64: addu r2,r2,r3
001c2a68: addu r2,r2,r25
001c2a6c: lbu r18,0x0004(r2)
001c2a70: j 0x001c2a7c
001c2a74: nop

001c2a78: addu r18,r0,r0
001c2a7c: lh r4,0x007c(r19)
001c2a80: lh r5,0x0088(r19)
001c2a84: jal 0x001a8be0                 decode polygon point (no pointer to store? returns value in r4 unless r6 exists.)
001c2a88: addu r6,r18,r0
001c2a8c: sw r2,0x0040(r29)              store point
001c2a90: lh r4,0x0080(r19)
001c2a94: lh r5,0x008c(r19)
001c2a98: jal 0x001a8be0
001c2a9c: addu r6,r18,r0
001c2aa0: sw r2,0x0044(r29)              store point
001c2aa4: lh r4,0x0084(r19)
001c2aa8: lh r5,0x0090(r19)
001c2aac: jal 0x001a8be0
001c2ab0: addu r6,r18,r0
001c2ab4: sw r2,0x0048(r29)              store point
001c2ab8: lw r2,0x0008(r19)              
001c2abc: nop
001c2ac0: srl r17,r2,0x1c
001c2ac4: addiu r17,r17,-0x0001
001c2ac8: addiu r2,r0,-0x0001
001c2acc: beq r17,r2,0x001c2afc          ...?
001c2ad0: sll r2,r17,0x02
001c2ad4: addu r2,r2,r17
001c2ad8: sll r2,r2,0x05
001c2adc: lui r3,0x801c
001c2ae0: lw r3,-0x4084(r3)
001c2ae4: lw r24,0x05f8(r29)
001c2ae8: addu r2,r2,r3
001c2aec: addu r2,r2,r24
001c2af0: lbu r18,0x0004(r2)
001c2af4: j 0x001c2b00
001c2af8: nop

001c2afc: addu r18,r0,r0
001c2b00: lh r4,0x005c(r19)
001c2b04: lh r5,0x0060(r19)
001c2b08: jal 0x001a8be0
001c2b0c: addu r6,r18,r0
001c2b10: lhu r4,0x1a04(r22)
001c2b14: nop
001c2b18: addu r4,r4,r2
001c2b1c: andi r4,r4,0x0fff
001c2b20: jal 0x0001bb5c                    sin r4
001c2b24: sh r4,0x1a04(r22)
001c2b28: lh r4,0x1a04(r22)                 
001c2b2c: addu r21,r2,r0
001c2b30: jal 0x0001bb5c                    sin r4
001c2b34: addiu r4,r4,0x0200
001c2b38: lh r4,0x1a04(r22)
001c2b3c: jal 0x0001bc28                    cosine r4
001c2b40: addu r20,r2,r0
001c2b44: addu r17,r0,r0
001c2b48: lh r4,0x1a04(r22)
001c2b4c: addu r18,r2,r0
001c2b50: jal 0x0001bc28                    cosine r4
001c2b54: addiu r4,r4,0x0200
001c2b58: addu r5,r2,r0
001c2b5c: addu r10,r0,r0
001c2b60: addu r8,r0,r0

001c2b64: lw r2,0x1a08(r22)
001c2b68: nop
001c2b6c: addu r2,r8,r2
001c2b70: sra r2,r2,0x08
001c2b74: addu r2,r16,r2
001c2b78: mult r18,r2
001c2b7c: addiu r3,r29,0x0050
001c2b80: sll r2,r17,0x07
001c2b84: addu r3,r3,r2
001c2b88: mflo r2
001c2b8c: sra r2,r2,0x0c
001c2b90: sw r2,0x0028(r3)
001c2b94: sw r2,0x0000(r3)
001c2b98: subu r2,r0,r2
001c2b9c: sw r2,0x0068(r3)
001c2ba0: sw r2,0x0040(r3)
001c2ba4: lw r2,0x1a08(r22)
001c2ba8: nop
001c2bac: addu r2,r8,r2
001c2bb0: sra r2,r2,0x08
001c2bb4: addu r2,r16,r2
001c2bb8: mult r21,r2
001c2bbc: mflo r2
001c2bc0: sra r2,r2,0x0c
001c2bc4: sw r2,0x0060(r3)
001c2bc8: sw r2,0x0008(r3)
001c2bcc: subu r2,r0,r2
001c2bd0: sw r2,0x0048(r3)
001c2bd4: sw r2,0x0020(r3)
001c2bd8: lw r2,0x1a08(r22)
001c2bdc: nop
001c2be0: addu r2,r8,r2
001c2be4: sra r2,r2,0x08
001c2be8: addu r2,r16,r2
001c2bec: mult r5,r2
001c2bf0: mflo r2
001c2bf4: sra r2,r2,0x0c
001c2bf8: sw r2,0x0038(r3)
001c2bfc: sw r2,0x0010(r3)
001c2c00: subu r2,r0,r2
001c2c04: sw r2,0x0078(r3)
001c2c08: sw r2,0x0050(r3)
001c2c0c: lw r2,0x1a08(r22)
001c2c10: nop
001c2c14: addu r2,r8,r2
001c2c18: sra r2,r2,0x08
001c2c1c: addu r2,r16,r2
001c2c20: mult r20,r2
001c2c24: addiu r17,r17,0x0001
001c2c28: sra r2,r10,0x08
001c2c2c: sw r2,0x0074(r3)
001c2c30: sw r2,0x0064(r3)
001c2c34: sw r2,0x0054(r3)
001c2c38: sw r2,0x0044(r3)
001c2c3c: sw r2,0x0034(r3)
001c2c40: sw r2,0x0024(r3)
001c2c44: sw r2,0x0014(r3)
001c2c48: sw r2,0x0004(r3)
001c2c4c: mflo r2
001c2c50: sra r2,r2,0x0c
001c2c54: sw r2,0x0070(r3)
001c2c58: sw r2,0x0018(r3)
001c2c5c: subu r2,r0,r2
001c2c60: sw r2,0x0058(r3)
001c2c64: sw r2,0x0030(r3)
001c2c68: lw r4,0x0034(r29)
001c2c6c: lw r2,0x0044(r29)
001c2c70: lw r3,0x0048(r29)
001c2c74: addu r4,r4,r2
001c2c78: lw r2,0x0038(r29)
001c2c7c: sw r4,0x0034(r29)
001c2c80: addu r2,r2,r3
001c2c84: addu r8,r8,r2
001c2c88: sw r2,0x0038(r29)
001c2c8c: slti r2,r17,0x0009
001c2c90: bne r2,r0,0x001c2b64           ^ loop
001c2c94: addu r10,r10,r4

001c2c98: lui r16,0x800a
001c2c9c: addiu r16,r16,-0x75dc
001c2ca0: lw r3,0x1a0c(r22)
001c2ca4: lw r2,0x0040(r29)
001c2ca8: addu r4,r16,r0
001c2cac: addu r3,r3,r2
001c2cb0: sw r3,0x1a0c(r22)
001c2cb4: lw r2,0x0030(r29)
001c2cb8: lw r5,0x1a08(r22)
001c2cbc: addu r2,r2,r3
001c2cc0: addu r2,r2,r5
001c2cc4: jal 0x0001d0a8                  Store Rotation matrix elements to GTE
001c2cc8: sw r2,0x1a08(r22)
001c2ccc: jal 0x0001d138                  Store Translation Vectors to GTE
001c2cd0: addu r4,r16,r0
001c2cd4: addiu r4,r29,0x0010             model data to transform in r4
001c2cd8: lw r16,0x05b0(r29)              load corners from stack
001c2cdc: lhu r2,0x0050(r29)
001c2ce0: lw r23,0x0000(r22)
001c2ce4: lw r11,0x05b4(r29)
001c2ce8: lw r9,0x05b8(r29)
001c2cec: lhu r3,0x0058(r29)
001c2cf0: addu r2,r2,r16
001c2cf4: sh r2,0x0010(r29)
001c2cf8: lhu r2,0x0054(r29)
001c2cfc: addu r3,r3,r9
001c2d00: sh r3,0x0014(r29)
001c2d04: addu r2,r2,r11
001c2d08: sh r2,0x0012(r29)
001c2d0c: addu r12,r4,r0
001c2d10: lwc2 gtedr00_vxy0,0x0000(r12)    move vxy0 vector from stack to gte coprocessor
001c2d14: lwc2 gtedr01_vz0,0x0004(r12)     ditto for vz0
001c2d18: nop
001c2d1c: nop
001c2d20: mvmva 0x1,0x0,0x0,0x0,0x0
001c2d24: addiu r2,r29,0x04f0
001c2d28: addu r12,r2,r0
001c2d2c: swc2 gtedr25_mac1,0x0000(r12)
001c2d30: swc2 gtedr26_mac2,0x0004(r12)
001c2d34: swc2 gtedr27_mac3,0x0008(r12)
001c2d38: addiu r2,r29,0x04fc
001c2d3c: addu r12,r2,r0
001c2d40: cfc2 r13,gtecr31_flag
001c2d44: nop
001c2d48: sw r13,0x0000(r12)
001c2d4c: sll r2,r23,0x01
001c2d50: addu r2,r2,r23
001c2d54: sll r2,r2,0x02
001c2d58: addu r2,r2,r23
001c2d5c: sll r2,r2,0x08
001c2d60: addiu r2,r2,0x0004
001c2d64: lhu r3,0x04f0(r29)
001c2d68: addu r6,r22,r2 
001c2d6c: sh r3,0x0020(r6)                      Store polygon YYY3
001c2d70: lhu r2,0x04f4(r29)
001c2d74: nop
001c2d78: sh r2,0x0022(r6)                      Store polygon XXX3
001c2d7c: lhu r2,0x0060(r29)
001c2d80: lhu r3,0x04f8(r29)
001c2d84: addu r2,r2,r16
001c2d88: sh r2,0x0010(r29)
001c2d8c: lhu r2,0x0064(r29)
001c2d90: sh r3,0x0510(r29)
001c2d94: lhu r3,0x0068(r29)
001c2d98: addu r2,r2,r11
001c2d9c: addu r3,r3,r9
001c2da0: sh r2,0x0012(r29)
001c2da4: sh r3,0x0014(r29)
001c2da8: addu r12,r4,r0
001c2dac: lwc2 gtedr00_vxy0,0x0000(r12)
001c2db0: lwc2 gtedr01_vz0,0x0004(r12)
001c2db4: nop
001c2db8: nop
001c2dbc: mvmva 0x1,0x0,0x0,0x0,0x0
001c2dc0: addiu r2,r29,0x0500
001c2dc4: addu r12,r2,r0
001c2dc8: swc2 gtedr25_mac1,0x0000(r12)
001c2dcc: swc2 gtedr26_mac2,0x0004(r12)
001c2dd0: swc2 gtedr27_mac3,0x0008(r12)
001c2dd4: addiu r2,r29,0x050c
001c2dd8: addu r12,r2,r0
001c2ddc: cfc2 r13,gtecr31_flag
001c2de0: nop
001c2de4: sw r13,0x0000(r12)
001c2de8: lhu r2,0x0500(r29)
001c2dec: nop
001c2df0: sh r2,0x002c(r6)                      store YYY4
001c2df4: lhu r2,0x0504(r29)
001c2df8: nop
001c2dfc: sh r2,0x002e(r6)                      store XXX4
001c2e00: lhu r2,0x00d0(r29)
001c2e04: lhu r3,0x0508(r29)
001c2e08: addu r2,r2,r16
001c2e0c: sh r2,0x0010(r29)
001c2e10: lhu r2,0x00d4(r29)
001c2e14: sh r3,0x0512(r29)
001c2e18: lhu r3,0x00d8(r29)
001c2e1c: addu r2,r2,r11
001c2e20: addu r3,r3,r9
001c2e24: sh r2,0x0012(r29)
001c2e28: sh r3,0x0014(r29)
001c2e2c: addu r12,r4,r0
001c2e30: lwc2 gtedr00_vxy0,0x0000(r12)
001c2e34: lwc2 gtedr01_vz0,0x0004(r12)
001c2e38: nop
001c2e3c: nop
001c2e40: mvmva 0x1,0x0,0x0,0x0,0x0
001c2e44: addiu r2,r29,0x04d0
001c2e48: addu r12,r2,r0
001c2e4c: swc2 gtedr25_mac1,0x0000(r12)
001c2e50: swc2 gtedr26_mac2,0x0004(r12)
001c2e54: swc2 gtedr27_mac3,0x0008(r12)
001c2e58: addiu r2,r29,0x04dc
001c2e5c: addu r12,r2,r0
001c2e60: cfc2 r13,gtecr31_flag
001c2e64: nop
001c2e68: sw r13,0x0000(r12)
001c2e6c: lhu r2,0x04d0(r29)
001c2e70: nop
001c2e74: sh r2,0x0008(r6)                         store YYY1
001c2e78: lhu r2,0x04d4(r29)
001c2e7c: nop
001c2e80: sh r2,0x000a(r6)                         store XXX1
001c2e84: lhu r2,0x00e0(r29)
001c2e88: lhu r3,0x04d8(r29)
001c2e8c: addu r2,r2,r16
001c2e90: sh r2,0x0010(r29)
001c2e94: lhu r2,0x00e4(r29)
001c2e98: sh r3,0x0520(r29)
001c2e9c: lhu r3,0x00e8(r29)
001c2ea0: addu r2,r2,r11
001c2ea4: addu r3,r3,r9
001c2ea8: sh r2,0x0012(r29)
001c2eac: sh r3,0x0014(r29)
001c2eb0: addu r12,r4,r0
001c2eb4: lwc2 gtedr00_vxy0,0x0000(r12)
001c2eb8: lwc2 gtedr01_vz0,0x0004(r12)
001c2ebc: nop
001c2ec0: nop
001c2ec4: mvmva 0x1,0x0,0x0,0x0,0x0
001c2ec8: addiu r2,r29,0x04e0
001c2ecc: addu r12,r2,r0
001c2ed0: swc2 gtedr25_mac1,0x0000(r12)
001c2ed4: swc2 gtedr26_mac2,0x0004(r12)
001c2ed8: swc2 gtedr27_mac3,0x0008(r12)
001c2edc: addiu r2,r29,0x04ec
001c2ee0: addu r12,r2,r0
001c2ee4: cfc2 r13,gtecr31_flag
001c2ee8: nop
001c2eec: sw r13,0x0000(r12)
001c2ef0: ori r17,r0,0x0002
001c2ef4: lhu r2,0x04e0(r29)
001c2ef8: addu r8,r6,r0
001c2efc: sh r2,0x0014(r8)                     store YYY2
001c2f00: lhu r2,0x04e4(r29)
001c2f04: addiu r5,r29,0x0014
001c2f08: sh r2,0x0016(r8)                     store XXX2
001c2f0c: lhu r2,0x04e8(r29)
001c2f10: ori r7,r0,0x0034                     polygt4 polygon
001c2f14: sh r2,0x0522(r29)
001c2f18: lhu r2,0x04e0(r29)

001c2f1c: addu r6,r8,r7                        pointer to next polygon
001c2f20: sh r2,0x0008(r6)                     store next polygon's YYY1
001c2f24: lhu r2,0x04e4(r29)
001c2f28: nop
001c2f2c: sh r2,0x000a(r6)                     " XXX2
001c2f30: lhu r2,0x0500(r29)
001c2f34: nop
001c2f38: sh r2,0x0020(r6)
001c2f3c: lhu r2,0x0504(r29)
001c2f40: addiu r3,r29,0x0050
001c2f44: sh r2,0x0022(r6)                       
001c2f48: sll r2,r17,0x04
001c2f4c: addu r3,r3,r2
001c2f50: lhu r2,0x0000(r3)
001c2f54: nop
001c2f58: addu r2,r2,r16
001c2f5c: sh r2,0x0010(r29)
001c2f60: lhu r2,0x0004(r3)
001c2f64: nop
001c2f68: addu r2,r2,r11
001c2f6c: sh r2,0x0012(r29)
001c2f70: lhu r2,0x0008(r3)
001c2f74: nop
001c2f78: addu r2,r2,r9
001c2f7c: sh r2,0x0014(r29)
001c2f80: addu r12,r4,r0
001c2f84: lwc2 gtedr00_vxy0,0x0000(r12)
001c2f88: lwc2 gtedr01_vz0,0x0004(r12)
001c2f8c: nop
001c2f90: nop
001c2f94: mvmva 0x1,0x0,0x0,0x0,0x0
001c2f98: addiu r2,r29,0x0500
001c2f9c: addu r12,r2,r0
001c2fa0: swc2 gtedr25_mac1,0x0000(r12)
001c2fa4: swc2 gtedr26_mac2,0x0004(r12)
001c2fa8: swc2 gtedr27_mac3,0x0008(r12)
001c2fac: addiu r2,r29,0x050c
001c2fb0: addu r12,r2,r0
001c2fb4: cfc2 r13,gtecr31_flag
001c2fb8: nop
001c2fbc: sw r13,0x0000(r12)
001c2fc0: lhu r2,0x0500(r29)
001c2fc4: nop
001c2fc8: sh r2,0x002c(r6)
001c2fcc: lhu r2,0x0504(r29)
001c2fd0: nop
001c2fd4: sh r2,0x002e(r6)
001c2fd8: lhu r2,0x0508(r29)
001c2fdc: nop
001c2fe0: sh r2,0x0500(r5)
001c2fe4: lhu r2,0x0080(r3)
001c2fe8: nop
001c2fec: addu r2,r2,r16
001c2ff0: sh r2,0x0010(r29)
001c2ff4: lhu r2,0x0084(r3)
001c2ff8: nop
001c2ffc: addu r2,r2,r11
001c3000: sh r2,0x0012(r29)
001c3004: lhu r2,0x0088(r3)
001c3008: nop
001c300c: addu r2,r2,r9
001c3010: sh r2,0x0014(r29)
001c3014: addu r12,r4,r0
001c3018: lwc2 gtedr00_vxy0,0x0000(r12)
001c301c: lwc2 gtedr01_vz0,0x0004(r12)
001c3020: nop
001c3024: nop
001c3028: mvmva 0x1,0x0,0x0,0x0,0x0
001c302c: addiu r2,r29,0x04e0
001c3030: addu r12,r2,r0
001c3034: swc2 gtedr25_mac1,0x0000(r12)
001c3038: swc2 gtedr26_mac2,0x0004(r12)
001c303c: swc2 gtedr27_mac3,0x0008(r12)
001c3040: addiu r2,r29,0x04ec
001c3044: addu r12,r2,r0
001c3048: cfc2 r13,gtecr31_flag
001c304c: nop
001c3050: sw r13,0x0000(r12)
001c3054: lhu r2,0x04e0(r29)
001c3058: nop
001c305c: sh r2,0x0014(r6)
001c3060: lhu r2,0x04e4(r29)
001c3064: addiu r7,r7,0x0034
001c3068: sh r2,0x0016(r6)
001c306c: lhu r2,0x04e8(r29)
001c3070: addiu r17,r17,0x0001
001c3074: sh r2,0x0510(r5)
001c3078: slti r2,r17,0x0008
001c307c: bne r2,r0,0x001c2f18             ^ loop

001c3080: addiu r5,r5,0x0002
001c3084: sll r2,r23,0x01
001c3088: addu r2,r2,r23
001c308c: sll r2,r2,0x02
001c3090: addu r2,r2,r23
001c3094: sll r2,r2,0x08
001c3098: addiu r2,r2,0x0004
001c309c: addu r2,r22,r2
001c30a0: addu r5,r2,r0
001c30a4: ori r18,r0,0x0001
001c30a8: addiu r20,r29,0x0010
001c30ac: addu r7,r5,r0
001c30b0: lhu r2,0x04e0(r29)
001c30b4: ori r25,r0,0x016c
001c30b8: sw r25,0x0630(r29)
001c30bc: sw r0,0x0638(r29)
001c30c0: sh r2,0x0174(r7)
001c30c4: lhu r2,0x04e4(r29)
001c30c8: ori r24,r0,0x030c
001c30cc: sw r24,0x0640(r29)
001c30d0: sh r2,0x0176(r7)
001c30d4: lhu r2,0x0500(r29)
001c30d8: ori r25,r0,0x01a0
001c30dc: sw r25,0x0650(r29)
001c30e0: sh r2,0x018c(r7)
001c30e4: lhu r2,0x0504(r29)
001c30e8: ori r21,r0,0x0020
001c30ec: sh r2,0x018e(r7)
001c30f0: lhu r2,0x0008(r7)
001c30f4: lhu r3,0x000a(r7)
001c30f8: lhu r4,0x0020(r7)
001c30fc: lhu r5,0x0022(r7)                        
001c3100: addu r30,r0,r0
001c3104: sh r2,0x0180(r7)
001c3108: sh r3,0x0182(r7)
001c310c: sh r4,0x0198(r7)
001c3110: sh r5,0x019a(r7)

001c3114: addiu r10,r18,0x0001
001c3118: sll r2,r10,0x07
001c311c: addiu r3,r29,0x0050
001c3120: addu r3,r3,r2
001c3124: lhu r2,0x0000(r3)
001c3128: nop
001c312c: addu r2,r2,r16
001c3130: sh r2,0x0010(r29)
001c3134: lhu r2,0x0004(r3)
001c3138: nop
001c313c: addu r2,r2,r11
001c3140: sh r2,0x0012(r29)
001c3144: lhu r2,0x0008(r3)
001c3148: nop
001c314c: addu r2,r2,r9
001c3150: sh r2,0x0014(r29)
001c3154: addu r12,r20,r0
001c3158: lwc2 gtedr00_vxy0,0x0000(r12)
001c315c: lwc2 gtedr01_vz0,0x0004(r12)
001c3160: nop
001c3164: nop
001c3168: mvmva 0x1,0x0,0x0,0x0,0x0
001c316c: addiu r2,r29,0x04d0
001c3170: addu r12,r2,r0
001c3174: swc2 gtedr25_mac1,0x0000(r12)
001c3178: swc2 gtedr26_mac2,0x0004(r12)
001c317c: swc2 gtedr27_mac3,0x0008(r12)
001c3180: addiu r2,r29,0x04dc
001c3184: addu r12,r2,r0
001c3188: cfc2 r13,gtecr31_flag
001c318c: nop
001c3190: sw r13,0x0000(r12)
001c3194: lw r24,0x0650(r29)
001c3198: lhu r2,0x04d0(r29)
001c319c: addu r6,r7,r24
001c31a0: sh r2,0x0008(r6)
001c31a4: lhu r2,0x04d4(r29)
001c31a8: addiu r4,r29,0x0510
001c31ac: sh r2,0x000a(r6)
001c31b0: lhu r2,0x04d8(r29)
001c31b4: addu r4,r4,r21
001c31b8: sh r2,0x0000(r4)
001c31bc: lhu r2,0x0010(r3)
001c31c0: nop
001c31c4: addu r2,r2,r16
001c31c8: sh r2,0x0010(r29)
001c31cc: lhu r2,0x0014(r3)
001c31d0: nop
001c31d4: addu r2,r2,r11
001c31d8: sh r2,0x0012(r29)
001c31dc: lhu r2,0x0018(r3)
001c31e0: nop
001c31e4: addu r2,r2,r9
001c31e8: sh r2,0x0014(r29)
001c31ec: addu r12,r20,r0
001c31f0: lwc2 gtedr00_vxy0,0x0000(r12)
001c31f4: lwc2 gtedr01_vz0,0x0004(r12)
001c31f8: nop
001c31fc: nop
001c3200: mvmva 0x1,0x0,0x0,0x0,0x0
001c3204: addiu r2,r29,0x04e0
001c3208: addu r12,r2,r0
001c320c: swc2 gtedr25_mac1,0x0000(r12)
001c3210: swc2 gtedr26_mac2,0x0004(r12)
001c3214: swc2 gtedr27_mac3,0x0008(r12)
001c3218: addiu r2,r29,0x04ec
001c321c: addu r12,r2,r0
001c3220: cfc2 r13,gtecr31_flag
001c3224: nop
001c3228: sw r13,0x0000(r12)
001c322c: lhu r2,0x04e0(r29)
001c3230: nop
001c3234: sh r2,0x0014(r6)
001c3238: lhu r2,0x04e4(r29)
001c323c: nop
001c3240: sh r2,0x0016(r6)
001c3244: lw r25,0x0638(r29)
001c3248: lhu r2,0x04e8(r29)
001c324c: addu r5,r7,r25
001c3250: sh r2,0x0002(r4)
001c3254: lhu r2,0x0008(r5)
001c3258: nop
001c325c: sh r2,0x0020(r6)
001c3260: lhu r2,0x000a(r5)
001c3264: nop
001c3268: sh r2,0x0022(r6)
001c326c: lhu r2,0x0014(r5)
001c3270: ori r17,r0,0x0002
001c3274: sw r30,0x0648(r29)
001c3278: sh r2,0x002c(r6)
001c327c: addu r2,r21,r20
001c3280: lhu r3,0x0016(r5)
001c3284: addiu r8,r2,0x0504
001c3288: sh r3,0x002e(r6)

001c328c: sll r3,r18,0x03
001c3290: addu r3,r3,r17
001c3294: sll r2,r3,0x01
001c3298: addu r2,r2,r3
001c329c: sll r2,r2,0x02
001c32a0: addu r2,r2,r3
001c32a4: sll r2,r2,0x02
001c32a8: addiu r2,r2,-0x0034
001c32ac: lhu r3,0x04e0(r29)
001c32b0: addu r6,r7,r2
001c32b4: sh r3,0x0008(r6)
001c32b8: lw r24,0x0648(r29)
001c32bc: nop
001c32c0: addu r3,r24,r17
001c32c4: sll r2,r3,0x01
001c32c8: addu r2,r2,r3
001c32cc: sll r2,r2,0x02
001c32d0: addu r2,r2,r3
001c32d4: sll r2,r2,0x02
001c32d8: addiu r2,r2,-0x0034
001c32dc: lhu r3,0x04e4(r29)
001c32e0: addu r5,r7,r2
001c32e4: sh r3,0x000a(r6)
001c32e8: lhu r2,0x0008(r5)
001c32ec: nop
001c32f0: sh r2,0x0020(r6)
001c32f4: lhu r2,0x000a(r5)
001c32f8: nop
001c32fc: sh r2,0x0022(r6)
001c3300: lhu r2,0x0014(r5)
001c3304: addiu r4,r29,0x0050
001c3308: sh r2,0x002c(r6)
001c330c: lhu r2,0x0016(r5)
001c3310: sll r3,r17,0x04
001c3314: sh r2,0x002e(r6)
001c3318: sll r2,r10,0x07
001c331c: addu r3,r3,r2
001c3320: addu r4,r4,r3
001c3324: lhu r2,0x0000(r4)
001c3328: nop
001c332c: addu r2,r2,r16
001c3330: sh r2,0x0010(r29)
001c3334: lhu r2,0x0004(r4)
001c3338: nop
001c333c: addu r2,r2,r11
001c3340: sh r2,0x0012(r29)
001c3344: lhu r2,0x0008(r4)
001c3348: nop
001c334c: addu r2,r2,r9
001c3350: sh r2,0x0014(r29)
001c3354: addu r12,r20,r0
001c3358: lwc2 gtedr00_vxy0,0x0000(r12)
001c335c: lwc2 gtedr01_vz0,0x0004(r12)
001c3360: nop
001c3364: nop
001c3368: mvmva 0x1,0x0,0x0,0x0,0x0
001c336c: addiu r2,r29,0x04e0
001c3370: addu r12,r2,r0
001c3374: swc2 gtedr25_mac1,0x0000(r12)
001c3378: swc2 gtedr26_mac2,0x0004(r12)
001c337c: swc2 gtedr27_mac3,0x0008(r12)
001c3380: addiu r2,r29,0x04ec
001c3384: addu r12,r2,r0
001c3388: cfc2 r13,gtecr31_flag
001c338c: nop
001c3390: sw r13,0x0000(r12)
001c3394: lhu r2,0x04e0(r29)
001c3398: nop
001c339c: sh r2,0x0014(r6)
001c33a0: lhu r2,0x04e4(r29)
001c33a4: nop
001c33a8: sh r2,0x0016(r6)
001c33ac: lhu r2,0x04e8(r29)
001c33b0: addiu r17,r17,0x0001
001c33b4: sh r2,0x0000(r8)
001c33b8: slti r2,r17,0x0008
001c33bc: bne r2,r0,0x001c328c         ^ loop
001c33c0: addiu r8,r8,0x0002

001c33c4: lw r25,0x0640(r29)
001c33c8: lw r24,0x0630(r29)
001c33cc: lhu r2,0x04e0(r29)
001c33d0: addu r6,r7,r25
001c33d4: addu r5,r7,r24
001c33d8: addiu r24,r24,0x01a0
001c33dc: sw r24,0x0630(r29)
001c33e0: sh r2,0x0008(r6)
001c33e4: lw r25,0x0638(r29)
001c33e8: lhu r2,0x04e4(r29)
001c33ec: addiu r25,r25,0x01a0
001c33f0: sw r25,0x0638(r29)
001c33f4: sh r2,0x000a(r6)
001c33f8: lw r24,0x0640(r29)
001c33fc: lhu r2,0x0008(r5)
001c3400: addiu r24,r24,0x01a0
001c3404: sw r24,0x0640(r29)
001c3408: sh r2,0x0020(r6)
001c340c: lhu r2,0x000a(r5)
001c3410: addiu r21,r21,0x0010
001c3414: sh r2,0x0022(r6)
001c3418: lhu r2,0x0014(r5)
001c341c: nop
001c3420: sh r2,0x002c(r6)
001c3424: lw r25,0x0650(r29)
001c3428: lhu r2,0x0016(r5)
001c342c: addu r5,r7,r25
001c3430: sh r2,0x002e(r6)
001c3434: lhu r2,0x0008(r5)
001c3438: addiu r18,r18,0x0001
001c343c: sh r2,0x0014(r6)
001c3440: lhu r2,0x000a(r5)
001c3444: addiu r25,r25,0x01a0
001c3448: sw r25,0x0650(r29)
001c344c: sh r2,0x0016(r6)
001c3450: slti r2,r18,0x0008
001c3454: bne r2,r0,0x001c3114          ^ loop
001c3458: addiu r30,r30,0x0008

001c345c: addu r17,r0,r0
001c3460: sll r3,r23,0x01
001c3464: addu r3,r3,r23
001c3468: sll r3,r3,0x02
001c346c: addu r3,r3,r23
001c3470: sll r3,r3,0x08
001c3474: addiu r3,r3,0x0004
001c3478: addu r3,r22,r3
001c347c: lbu r7,0x0600(r29)
001c3480: lw r24,0x0600(r29)
001c3484: lw r25,0x0610(r29)
001c3488: lhu r2,0x1a06(r22)
001c348c: addu r6,r24,r25
001c3490: sll r2,r2,0x10
001c3494: sra r18,r2,0x18
001c3498: lw r24,0x0608(r29)
001c349c: lw r25,0x0618(r29)
001c34a0: addu r5,r24,r18
001c34a4: addu r2,r24,r25
001c34a8: addu r4,r2,r18

polygon CLUT & TPAGE loop

001c34ac: sb r7,0x0024(r3)                     (buffer)
001c34b0: sb r7,0x000c(r3)                     store CLUT 
001c34b4: sb r5,0x0019(r3)                     store in tpage? (colour stored in sheet dedicated to effect?)
001c34b8: sb r5,0x000d(r3)                     store rest of CLUT
001c34bc: sb r6,0x0030(r3)                     (buffer)
001c34c0: sb r6,0x0018(r3)                     store TPAGE
001c34c4: sb r4,0x0031(r3)                     (buffer)
001c34c8: sb r4,0x0025(r3)
001c34cc: addiu r17,r17,0x0001
001c34d0: slti r2,r17,0x0040
001c34d4: bne r2,r0,0x001c34ac                  loop 0x40 times
001c34d8: addiu r3,r3,0x0034                    next polygon

001c34dc: lhu r2,0x0006(r19)
001c34e0: lh r10,0x003c(r19)
001c34e4: andi r2,r2,0x0040
001c34e8: beq r2,r0,0x001c3564
001c34ec: ori r14,r0,0x0080

001c34f0: lw r3,0x0010(r19)
001c34f4: lui r4,0x801c
001c34f8: lw r4,-0x4084(r4)
001c34fc: lw r24,0x05f8(r29)
001c3500: andi r8,r3,0x0fff
001c3504: andi r3,r3,0x000f
001c3508: sll r2,r3,0x02
001c350c: addu r2,r2,r3
001c3510: sll r2,r2,0x05
001c3514: addu r2,r2,r4
001c3518: addu r2,r2,r24
001c351c: sra r3,r8,0x04
001c3520: andi r3,r3,0x000f
001c3524: lbu r16,0x0004(r2)
001c3528: sll r2,r3,0x02
001c352c: addu r2,r2,r3
001c3530: sll r2,r2,0x05
001c3534: addu r2,r2,r4
001c3538: addu r2,r2,r24
001c353c: srl r3,r8,0x08
001c3540: lbu r15,0x0004(r2)
001c3544: sll r2,r3,0x02
001c3548: addu r2,r2,r3
001c354c: sll r2,r2,0x05
001c3550: addu r2,r2,r4
001c3554: addu r2,r2,r24
001c3558: lbu r14,0x0004(r2)
001c355c: j 0x001c3570
001c3560: sll r2,r10,0x03

001c3564: ori r15,r0,0x0080
001c3568: ori r16,r0,0x0080
001c356c: sll r2,r10,0x03
001c3570: addu r2,r2,r10
001c3574: sll r2,r2,0x02
001c3578: lui r1,0x801c
001c357c: addu r1,r1,r2
001c3580: lw r8,0x5174(r1)
001c3584: nop
001c3588: mult r8,r16
001c358c: mflo r4
001c3590: nop
001c3594: nop
001c3598: mult r8,r15
001c359c: mflo r3
001c35a0: nop
001c35a4: nop
001c35a8: mult r8,r14
001c35ac: addu r17,r0,r0
001c35b0: sll r2,r23,0x01
001c35b4: addu r2,r2,r23
001c35b8: sll r2,r2,0x02
001c35bc: addu r2,r2,r23
001c35c0: sll r2,r2,0x08
001c35c4: addiu r2,r2,0x0004
001c35c8: addu r5,r22,r2
001c35cc: srl r4,r4,0x0c
001c35d0: srl r3,r3,0x0c
001c35d4: mflo r2
001c35d8: srl r6,r2,0x0c
001c35dc: sb r4,0x0028(r5)
001c35e0: sb r4,0x001c(r5)
001c35e4: sb r3,0x0029(r5)
001c35e8: sb r3,0x001d(r5)
001c35ec: sb r6,0x002a(r5)
001c35f0: sb r6,0x001e(r5)
001c35f4: addiu r17,r17,0x0001
001c35f8: slti r2,r17,0x0008
001c35fc: bne r2,r0,0x001c35dc
001c3600: addiu r5,r5,0x0034
001c3604: addu r18,r0,r0
001c3608: sll r2,r23,0x01
001c360c: addu r2,r2,r23
001c3610: sll r2,r2,0x02
001c3614: addu r19,r2,r23
001c3618: ori r13,r0,0x0008
001c361c: lui r3,0x801c
001c3620: addiu r3,r3,0x5174
001c3624: sll r2,r10,0x03
001c3628: addu r2,r2,r10
001c362c: sll r2,r2,0x02
001c3630: addu r11,r2,r3

001c3634: lw r8,0x0004(r11)
001c3638: nop
001c363c: mult r8,r16
001c3640: mflo r2
001c3644: nop
001c3648: nop
001c364c: mult r8,r15
001c3650: addu r17,r0,r0
001c3654: sll r3,r19,0x08
001c3658: addiu r3,r3,0x0004
001c365c: addu r9,r22,r3
001c3660: addu r12,r13,r0
001c3664: srl r7,r2,0x0c
001c3668: mflo r2
001c366c: srl r4,r2,0x0c

001c3670: sll r3,r18,0x03
001c3674: addu r3,r3,r17
001c3678: sll r2,r3,0x01
001c367c: addu r2,r2,r3
001c3680: sll r2,r2,0x02
001c3684: addu r2,r2,r3
001c3688: sll r2,r2,0x02
001c368c: addu r6,r9,r2
001c3690: addu r3,r12,r17
001c3694: sll r2,r3,0x01
001c3698: addu r2,r2,r3
001c369c: sll r2,r2,0x02
001c36a0: addu r2,r2,r3
001c36a4: mult r8,r14
001c36a8: sll r2,r2,0x02
001c36ac: addu r5,r9,r2
001c36b0: addiu r17,r17,0x0001
001c36b4: sb r7,0x0028(r5)
001c36b8: sb r7,0x001c(r5)
001c36bc: sb r7,0x0010(r6)
001c36c0: sb r7,0x0004(r6)
001c36c4: sb r4,0x0029(r5)
001c36c8: sb r4,0x001d(r5)
001c36cc: sb r4,0x0011(r6)
001c36d0: sb r4,0x0005(r6)
001c36d4: mflo r2
001c36d8: srl r2,r2,0x0c
001c36dc: sb r2,0x002a(r5)
001c36e0: sb r2,0x001e(r5)
001c36e4: sb r2,0x0012(r6)
001c36e8: sb r2,0x0006(r6)
001c36ec: slti r2,r17,0x0008
001c36f0: bne r2,r0,0x001c3670       ^ loop
001c36f4: nop

001c36f8: addiu r13,r13,0x0008
001c36fc: addiu r18,r18,0x0001
001c3700: slti r2,r18,0x0007
001c3704: bne r2,r0,0x001c3634       ^ loop
001c3708: addiu r11,r11,0x0004

001c370c: sll r2,r10,0x03
001c3710: addu r2,r2,r10
001c3714: sll r2,r2,0x02
001c3718: lui r1,0x801c
001c371c: addu r1,r1,r2
001c3720: lw r8,0x5194(r1)
001c3724: nop
001c3728: mult r8,r16
001c372c: mflo r4
001c3730: nop
001c3734: nop
001c3738: mult r8,r15
001c373c: mflo r3
001c3740: nop
001c3744: nop
001c3748: mult r8,r14
001c374c: addu r17,r0,r0
001c3750: sll r2,r23,0x01
001c3754: addu r2,r2,r23
001c3758: sll r2,r2,0x02
001c375c: addu r2,r2,r23
001c3760: sll r2,r2,0x08
001c3764: addiu r2,r2,0x0004
001c3768: ori r5,r0,0x0b60
001c376c: srl r4,r4,0x0c
001c3770: addu r8,r22,r2
001c3774: srl r3,r3,0x0c
001c3778: mflo r2
001c377c: srl r7,r2,0x0c
001c3780: addu r6,r8,r5
001c3784: addiu r5,r5,0x0034
001c3788: addiu r17,r17,0x0001
001c378c: slti r2,r17,0x0008
001c3790: sb r4,0x0010(r6)
001c3794: sb r4,0x0004(r6)
001c3798: sb r3,0x0011(r6)
001c379c: sb r3,0x0005(r6)
001c37a0: sb r7,0x0012(r6)
001c37a4: bne r2,r0,0x001c3780       ^ loop
001c37a8: sb r7,0x0006(r6)

001c37ac: addu r18,r0,r0
001c37b0: addiu r16,r29,0x0010
001c37b4: addiu r15,r29,0x0520
001c37b8: sll r2,r23,0x01
001c37bc: addu r2,r2,r23
001c37c0: sll r2,r2,0x02
001c37c4: addu r14,r2,r23
001c37c8: addu r17,r0,r0
001c37cc: lui r9,0x00ff
001c37d0: ori r9,r9,0xffff
001c37d4: lui r12,0xff00
001c37d8: sll r11,r14,0x08
001c37dc: addiu r2,r11,0x0004
001c37e0: addu r13,r22,r2
001c37e4: sll r2,r18,0x04
001c37e8: addu r8,r15,r2
001c37ec: addu r2,r2,r16
001c37f0: addiu r7,r2,0x0500

001c37f4: lh r2,0x0000(r7)
001c37f8: lh r3,0x0002(r7)
001c37fc: nop
001c3800: addu r2,r2,r3
001c3804: lh r3,0x0000(r8)
001c3808: lh r4,0x0002(r8)
001c380c: addu r2,r2,r3
001c3810: addu r2,r2,r4
001c3814: bgez r2,0x001c3824
001c3818: sra r10,r2,0x04
001c381c: addiu r2,r2,0x000f
001c3820: sra r10,r2,0x04
001c3824: sltiu r2,r10,0x0180
001c3828: beq r2,r0,0x001c3890
001c382c: addiu r8,r8,0x0002
001c3830: sll r2,r18,0x03
001c3834: addu r2,r2,r17
001c3838: sll r4,r2,0x01
001c383c: addu r4,r4,r2
001c3840: sll r4,r4,0x02
001c3844: addu r4,r4,r2
001c3848: sll r4,r4,0x02
001c384c: addu r6,r11,r22
001c3850: addu r6,r4,r6
001c3854: sll r5,r10,0x02
001c3858: addu r4,r13,r4
001c385c: lw r25,0x0620(r29)                  load otag list
001c3860: lw r2,0x0004(r6)
001c3864: addu r5,r5,r25
001c3868: lw r3,0x0000(r5)
001c386c: and r2,r2,r12
001c3870: and r3,r3,r9
001c3874: or r2,r2,r3
001c3878: sw r2,0x0004(r6)
001c387c: lw r2,0x0000(r5)
001c3880: and r4,r4,r9
001c3884: and r2,r2,r12
001c3888: or r2,r2,r4
001c388c: sw r2,0x0000(r5)
001c3890: addiu r17,r17,0x0001
001c3894: slti r2,r17,0x0007
001c3898: bne r2,r0,0x001c37f4        ^ loop
001c389c: addiu r7,r7,0x0002

001c38a0: sll r2,r18,0x04
001c38a4: addiu r3,r29,0x0510
001c38a8: addu r2,r3,r2
001c38ac: lh r4,0x0000(r2)
001c38b0: lh r2,0x000e(r2)
001c38b4: addiu r11,r18,0x0001
001c38b8: addu r4,r4,r2
001c38bc: sll r2,r11,0x04
001c38c0: addu r3,r3,r2
001c38c4: lh r2,0x0000(r3)
001c38c8: lh r3,0x000e(r3)
001c38cc: addu r4,r4,r2
001c38d0: addu r2,r4,r3
001c38d4: bgez r2,0x001c38e4
001c38d8: sra r10,r2,0x04
001c38dc: addiu r2,r2,0x000f
001c38e0: sra r10,r2,0x04
001c38e4: sltiu r2,r10,0x0180
001c38e8: beq r2,r0,0x001c3960
001c38ec: lui r9,0x00ff
001c38f0: ori r9,r9,0xffff
001c38f4: sll r5,r14,0x08
001c38f8: addu r7,r5,r22
001c38fc: sll r4,r18,0x01
001c3900: addu r4,r4,r18
001c3904: sll r4,r4,0x02
001c3908: addu r4,r4,r18
001c390c: sll r4,r4,0x05
001c3910: addu r7,r7,r4
001c3914: sll r6,r10,0x02
001c3918: lui r8,0xff00
001c391c: addiu r5,r5,0x0004
001c3920: addu r5,r22,r5
001c3924: addiu r4,r4,0x016c
001c3928: addu r5,r5,r4
001c392c: lw r24,0x0620(r29)                   load otag list
001c3930: lw r3,0x0170(r7)
001c3934: addu r6,r6,r24
001c3938: lw r2,0x0000(r6)
001c393c: and r3,r3,r8
001c3940: and r2,r2,r9
001c3944: or r3,r3,r2
001c3948: sw r3,0x0170(r7)
001c394c: lw r2,0x0000(r6)
001c3950: and r5,r5,r9
001c3954: and r2,r2,r8
001c3958: or r2,r2,r5
001c395c: sw r2,0x0000(r6)
001c3960: addu r18,r11,r0
001c3964: slti r2,r11,0x0008
001c3968: bne r2,r0,0x001c37cc
001c396c: addu r17,r0,r0
001c3970: lw r3,0x0000(r22)
001c3974: ori r2,r0,0x0001
001c3978: subu r2,r2,r3
001c397c: j 0x001c39c4
001c3980: sw r2,0x0000(r22)

if 0x22 TED = 0x3 (end?)

001c3984: sll r2,r30,0x02
001c3988: addu r16,r2,r23
001c398c: lw r22,0x00e4(r16)
001c3990: nop
001c3994: lw r2,0x1a18(r22)
001c3998: nop
001c399c: bne r2,r0,0x001c39ac
001c39a0: nop
001c39a4: j 0x001c39c4
001c39a8: sw r4,0x1a18(r22)
001c39ac: beq r22,r0,0x001c39c0
001c39b0: nop
001c39b4: jal 0x001a4e9c
001c39b8: addu r4,r22,r0
001c39bc: sw r0,0x00e4(r16)                             clear model pointer
001c39c0: sb r0,0x0022(r17)                             set model phase to 0

End

001c39c4: lw r31,0x067c(r29)
001c39c8: lw r30,0x0678(r29)
001c39cc: lw r23,0x0674(r29)
001c39d0: lw r22,0x0670(r29)
001c39d4: lw r21,0x066c(r29)
001c39d8: lw r20,0x0668(r29)
001c39dc: lw r19,0x0664(r29)
001c39e0: lw r18,0x0660(r29)
001c39e4: lw r17,0x065c(r29)
001c39e8: lw r16,0x0658(r29)
001c39ec: addiu r29,r29,0x0680
001c39f0: jr r31
001c39f4: nop