Difference between revisions of "Load file into RAM"
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| − | Actually BIOS 2 CD_GetSector? doesn't load file according to documentation - | + | Actually BIOS 2 CD_GetSector? doesn't load file according to documentation - if the CDROM FIFO is the buffer mentioned in official documentation, that would support this being CDGetsector. |
00020650: 3c028003 lui r2,0x8003 | 00020650: 3c028003 lui r2,0x8003 | ||
| − | 00020654: 8c421b40 lw r2,0x1b40(r2) | + | 00020654: 8c421b40 lw r2,0x1b40(r2) # CDREG0 |
00020658: 3c060002 lui r6,0x0002 | 00020658: 3c060002 lui r6,0x0002 | ||
| − | 0002065c: a0400000 sb r0,0x0000(r2) | + | 0002065c: a0400000 sb r0,0x0000(r2) # un-index CDREG port |
00020660: 3c038003 lui r3,0x8003 | 00020660: 3c038003 lui r3,0x8003 | ||
| − | 00020664: 8c631b4c lw r3,0x1b4c(r3) | + | 00020664: 8c631b4c lw r3,0x1b4c(r3) # CDREG3 |
| − | 00020668: 34020080 ori r2,r0,0x0080 | + | 00020668: 34020080 ori r2,r0,0x0080 # |
| − | 0002066c: a0620000 sb r2,0x0000(r3) | + | 0002066c: a0620000 sb r2,0x0000(r3) # Store want data to CDREG3 |
00020670: 3c028003 lui r2,0x8003 | 00020670: 3c028003 lui r2,0x8003 | ||
| − | 00020674: 8c421b74 lw r2,0x1b74(r2) | + | 00020674: 8c421b74 lw r2,0x1b74(r2) # CDROM Delay/Size* |
| − | 00020678: 34c60943 ori r6,r6,0x0943 | + | 00020678: 34c60943 ori r6,r6,0x0943 # r6 = 0x00020943 |
| − | 0002067c: ac460000 sw r6,0x0000(r2) | + | 0002067c: ac460000 sw r6,0x0000(r2) # |
00020680: 3c038003 lui r3,0x8003 | 00020680: 3c038003 lui r3,0x8003 | ||
| − | 00020684: 8c631b50 lw r3,0x1b50(r3) | + | 00020684: 8c631b50 lw r3,0x1b50(r3) # common delay |
00020688: 34021323 ori r2,r0,0x1323 | 00020688: 34021323 ori r2,r0,0x1323 | ||
| − | 0002068c: ac620000 sw r2,0x0000(r3) | + | 0002068c: ac620000 sw r2,0x0000(r3) # 1323 common delay (1 recovery cycle, 3 hold cycles, 2 floating release cycles, 3 strobe active-going edge delay) |
00020690: 3c038003 lui r3,0x8003 | 00020690: 3c038003 lui r3,0x8003 | ||
| − | 00020694: 8c631b78 lw r3,0x1b78(r3) | + | 00020694: 8c631b78 lw r3,0x1b78(r3) # DPCR - DMA Control Register |
00020698: 00000000 nop | 00020698: 00000000 nop | ||
| − | 0002069c: 8c620000 lw r2,0x0000(r3) | + | 0002069c: 8c620000 lw r2,0x0000(r3) # |
000206a0: 00000000 nop | 000206a0: 00000000 nop | ||
| − | 000206a4: 34428000 ori r2,r2,0x8000 | + | 000206a4: 34428000 ori r2,r2,0x8000 # enable CDROM (don't change priority) |
| − | 000206a8: ac620000 sw r2,0x0000(r3) | + | 000206a8: ac620000 sw r2,0x0000(r3) # re-store |
000206ac: 3c028003 lui r2,0x8003 | 000206ac: 3c028003 lui r2,0x8003 | ||
| − | 000206b0: 8c421b7c lw r2,0x1b7c(r2) | + | 000206b0: 8c421b7c lw r2,0x1b7c(r2) # DMA CDROM channel |
000206b4: 00000000 nop | 000206b4: 00000000 nop | ||
| − | 000206b8: ac440000 sw r4,0x0000(r2) # store | + | 000206b8: ac440000 sw r4,0x0000(r2) # store memory address for DMA to write to |
| − | 000206bc: 3c020001 lui r2,0x0001 | + | 000206bc: 3c020001 lui r2,0x0001 # no particular use; conventionally means "one block" from CDROM. |
000206c0: 3c038003 lui r3,0x8003 | 000206c0: 3c038003 lui r3,0x8003 | ||
| − | 000206c4: 8c631b80 lw r3,0x1b80(r3) | + | 000206c4: 8c631b80 lw r3,0x1b80(r3) # DMA CDROM channel |
| − | 000206c8: 00a22825 or r5,r5,r2 # | + | 000206c8: 00a22825 or r5,r5,r2 # number of words |
| − | 000206cc: ac650000 sw r5,0x0000(r3) | + | 000206cc: ac650000 sw r5,0x0000(r3) # go, search, and transfer to ram |
000206d0: 3c038003 lui r3,0x8003 | 000206d0: 3c038003 lui r3,0x8003 | ||
| − | 000206d4: 8c631b40 lw r3,0x1b40(r3) | + | 000206d4: 8c631b40 lw r3,0x1b40(r3) # CDREG0 |
000206d8: 00000000 nop | 000206d8: 00000000 nop | ||
| − | 000206dc: 90620000 lbu r2,0x0000(r3) | + | 000206dc: 90620000 lbu r2,0x0000(r3) # |
000206e0: 00000000 nop | 000206e0: 00000000 nop | ||
| − | 000206e4: 30420040 andi r2,r2,0x0040 | + | 000206e4: 30420040 andi r2,r2,0x0040 # data FIFO empty |
| − | 000206e8: 1040fffb beq r2,r0,0x000206d8 | + | 000206e8: 1040fffb beq r2,r0,0x000206d8 # loop if data FIFO is still empty (or until it's done putting everything requested in the FIFO?) |
| − | 000206ec: 3c021100 lui r2,0x1100 | + | 000206ec: 3c021100 lui r2,0x1100 # start transfer, force transfer start without waiting for DREQ |
000206f0: 3c038003 lui r3,0x8003 | 000206f0: 3c038003 lui r3,0x8003 | ||
| − | 000206f4: 8c631b84 lw r3,0x1b84(r3) | + | 000206f4: 8c631b84 lw r3,0x1b84(r3) # CD ROM channel controll |
000206f8: 00000000 nop | 000206f8: 00000000 nop | ||
| − | 000206fc: ac620000 sw r2,0x0000(r3) | + | 000206fc: ac620000 sw r2,0x0000(r3) # start data transfer |
00020700: 3c048003 lui r4,0x8003 | 00020700: 3c048003 lui r4,0x8003 | ||
| − | 00020704: 8c841b84 lw r4,0x1b84(r4) | + | 00020704: 8c841b84 lw r4,0x1b84(r4) # CD ROM channel controll |
00020708: 00000000 nop | 00020708: 00000000 nop | ||
| − | 0002070c: 8c820000 lw r2,0x0000(r4) | + | 0002070c: 8c820000 lw r2,0x0000(r4) # |
| − | 00020710: 3c030100 lui r3,0x0100 | + | 00020710: 3c030100 lui r3,0x0100 # |
00020714: 00431024 and r2,r2,r3 | 00020714: 00431024 and r2,r2,r3 | ||
| − | 00020718: 10400007 beq r2,r0,0x00020738 | + | 00020718: 10400007 beq r2,r0,0x00020738 # break if CD rom data transfer not busy |
0002071c: 00801821 addu r3,r4,r0 | 0002071c: 00801821 addu r3,r4,r0 | ||
00020720: 3c040100 lui r4,0x0100 | 00020720: 3c040100 lui r4,0x0100 | ||
| Line 56: | Line 56: | ||
00020728: 00000000 nop | 00020728: 00000000 nop | ||
0002072c: 00441024 and r2,r2,r4 | 0002072c: 00441024 and r2,r2,r4 | ||
| − | 00020730: 1440fffc bne r2,r0,0x00020724 | + | 00020730: 1440fffc bne r2,r0,0x00020724 # loop if CD rom data transfer still busy |
00020734: 00000000 nop | 00020734: 00000000 nop | ||
00020738: 3c038003 lui r3,0x8003 | 00020738: 3c038003 lui r3,0x8003 | ||
| − | 0002073c: 8c631b50 lw r3,0x1b50(r3) | + | 0002073c: 8c631b50 lw r3,0x1b50(r3) # Common delay |
00020740: 34021325 ori r2,r0,0x1325 | 00020740: 34021325 ori r2,r0,0x1325 | ||
| − | 00020744: ac620000 sw r2,0x0000(r3) | + | 00020744: ac620000 sw r2,0x0000(r3) # store 1325 as common delay (1 recovery cycle, 3 hold cycles, 2 floating release cycles, 5 strobe active-going edge delay) |
00020748: 03e00008 jr r31 | 00020748: 03e00008 jr r31 | ||
| − | 0002074c: 00001021 addu r2,r0,r0 | + | 0002074c: 00001021 addu r2,r0,r0 # always return 0 |
| + | |||
| + | *r6 is made of the following bitflags to the CDROM: | ||
| + | 0x43: write delay 3 cycles, read delay 4 cycles. | ||
| + | 0x09: enable recovery period (0x1), enable pre-strobe period (0x8) | ||
| + | 0x20: memory window size 2^2 bytes (0x2) | ||
Latest revision as of 09:28, 6 June 2024
Actually BIOS 2 CD_GetSector? doesn't load file according to documentation - if the CDROM FIFO is the buffer mentioned in official documentation, that would support this being CDGetsector.
00020650: 3c028003 lui r2,0x8003 00020654: 8c421b40 lw r2,0x1b40(r2) # CDREG0 00020658: 3c060002 lui r6,0x0002 0002065c: a0400000 sb r0,0x0000(r2) # un-index CDREG port 00020660: 3c038003 lui r3,0x8003 00020664: 8c631b4c lw r3,0x1b4c(r3) # CDREG3 00020668: 34020080 ori r2,r0,0x0080 # 0002066c: a0620000 sb r2,0x0000(r3) # Store want data to CDREG3 00020670: 3c028003 lui r2,0x8003 00020674: 8c421b74 lw r2,0x1b74(r2) # CDROM Delay/Size* 00020678: 34c60943 ori r6,r6,0x0943 # r6 = 0x00020943 0002067c: ac460000 sw r6,0x0000(r2) # 00020680: 3c038003 lui r3,0x8003 00020684: 8c631b50 lw r3,0x1b50(r3) # common delay 00020688: 34021323 ori r2,r0,0x1323 0002068c: ac620000 sw r2,0x0000(r3) # 1323 common delay (1 recovery cycle, 3 hold cycles, 2 floating release cycles, 3 strobe active-going edge delay) 00020690: 3c038003 lui r3,0x8003 00020694: 8c631b78 lw r3,0x1b78(r3) # DPCR - DMA Control Register 00020698: 00000000 nop 0002069c: 8c620000 lw r2,0x0000(r3) # 000206a0: 00000000 nop 000206a4: 34428000 ori r2,r2,0x8000 # enable CDROM (don't change priority) 000206a8: ac620000 sw r2,0x0000(r3) # re-store 000206ac: 3c028003 lui r2,0x8003 000206b0: 8c421b7c lw r2,0x1b7c(r2) # DMA CDROM channel 000206b4: 00000000 nop 000206b8: ac440000 sw r4,0x0000(r2) # store memory address for DMA to write to 000206bc: 3c020001 lui r2,0x0001 # no particular use; conventionally means "one block" from CDROM. 000206c0: 3c038003 lui r3,0x8003 000206c4: 8c631b80 lw r3,0x1b80(r3) # DMA CDROM channel 000206c8: 00a22825 or r5,r5,r2 # number of words 000206cc: ac650000 sw r5,0x0000(r3) # go, search, and transfer to ram 000206d0: 3c038003 lui r3,0x8003 000206d4: 8c631b40 lw r3,0x1b40(r3) # CDREG0 000206d8: 00000000 nop 000206dc: 90620000 lbu r2,0x0000(r3) # 000206e0: 00000000 nop 000206e4: 30420040 andi r2,r2,0x0040 # data FIFO empty 000206e8: 1040fffb beq r2,r0,0x000206d8 # loop if data FIFO is still empty (or until it's done putting everything requested in the FIFO?) 000206ec: 3c021100 lui r2,0x1100 # start transfer, force transfer start without waiting for DREQ 000206f0: 3c038003 lui r3,0x8003 000206f4: 8c631b84 lw r3,0x1b84(r3) # CD ROM channel controll 000206f8: 00000000 nop 000206fc: ac620000 sw r2,0x0000(r3) # start data transfer 00020700: 3c048003 lui r4,0x8003 00020704: 8c841b84 lw r4,0x1b84(r4) # CD ROM channel controll 00020708: 00000000 nop 0002070c: 8c820000 lw r2,0x0000(r4) # 00020710: 3c030100 lui r3,0x0100 # 00020714: 00431024 and r2,r2,r3 00020718: 10400007 beq r2,r0,0x00020738 # break if CD rom data transfer not busy 0002071c: 00801821 addu r3,r4,r0 00020720: 3c040100 lui r4,0x0100 00020724: 8c620000 lw r2,0x0000(r3) 00020728: 00000000 nop 0002072c: 00441024 and r2,r2,r4 00020730: 1440fffc bne r2,r0,0x00020724 # loop if CD rom data transfer still busy 00020734: 00000000 nop 00020738: 3c038003 lui r3,0x8003 0002073c: 8c631b50 lw r3,0x1b50(r3) # Common delay 00020740: 34021325 ori r2,r0,0x1325 00020744: ac620000 sw r2,0x0000(r3) # store 1325 as common delay (1 recovery cycle, 3 hold cycles, 2 floating release cycles, 5 strobe active-going edge delay) 00020748: 03e00008 jr r31 0002074c: 00001021 addu r2,r0,r0 # always return 0
*r6 is made of the following bitflags to the CDROM: 0x43: write delay 3 cycles, read delay 4 cycles. 0x09: enable recovery period (0x1), enable pre-strobe period (0x8) 0x20: memory window size 2^2 bytes (0x2)
