IO Ports

all IO ports start with 0x1f8, and any mention of a toggleable flag is within the component itself, NOT in ram.

LIBSPU

8002ad44 - SPU voice IO port
       This is used generally as a pointer to the SPU voices, any voice left/right volume is accessed by ID, as well as some CD/external audio volume settings by addition. 
       Technically it literally points to voice_0 volume left.
8002ad48 - DMA SPU channel base address
8002ad4c - DMA SPU channel block control
8002ad50 - DMA SPU channel control
8002ad54 - DPCR - DMA Control Register
8002ad58 - SPU Delay/Size
       0x8000 0000: Wait (whether to wait for external device)
       0x4000 0000: Wide DMA (whether to use 32 bit data bus width)
       0x2000 0000: DMA Timing select (whether to override timing with 0x0f00 0000)
       0x1000 0000: Address error flag
       0x0f00 0000: DMA Timing override
       0x00f0 0000: always 0
       0x000f 0000: Number of address bits
       0x0000 c000: unknown
       0x0000 2000: Auto Increment
       0x0000 1000: Data Bus Width (0 = 8 bit, 1 = 16 bit, only if not 0x4000 0000)
       0x0000 0800: pre-strobe period (using COM3 timing)
       0x0000 0400: floating period (using COM2 timing)
       0x0000 0200: Hold Period (using COM1 timing)
       0x0000 0100: Recovery Period (using COM0 timing)
       0x0000 00f0: Read delay
       0x0000 000f: Write delay

LIBGTE

800306ec - GP1 - GPU Display Control & Status register
800306f0 - HBLANK.0 - HBlank timer
800306f4 - Horizontal Retrace Counter Start? (gets subtracted from the counter)

LIBC

80031788 - I_STAT - Interrupt status register
8003178c - I_MASK - Interrupt mask register
80031790 - DPCR - DMA Control Register

800317bc - HBLANK.4 - HBlank timer mode
       0xffff 0000: garbage
       0x0000 e000: unknown
       0x0000 1000: reached 0xffff
       0x0000 0800: reached target value
       0x0000 0400: interrupt request
       0x0000 0300: Clock source (0, 2: System clock, 1, 3: Hblank)
       0x0000 0080: IRQ pulse/toggle mode (whether interrupt request pulsed off then on (0) or is toggled on/off (1))
       0x0000 0040: IRQ once/repeat mode
       0x0000 0020: IRQ when counter = 0xffff
       0x0000 0010: IRQ when counter =  target value
       0x0000 0008: reset mode (set counter to 0 when meet 0xffff (0) or target value (1))
       0x0000 0006: synchronisation mode
       0x0000 0001: synchronisation enable
800317c0 - DICR - DMA Interrupt Register

800317e4 - DMA MDECin base address

800317ec - HSTS (read)/ADDRESS (write) - CD Index/Status register
       bit 0 - 1: Read/Writeable
       bit 2 - 7: Read Only
800317f0 - cdreg1 address
       Read (any bank): RESULT - CD Response FIFO
       Write (bank 0) : COMMAND - CD Command register
       Write (bank 1) : WRDATA - unknown? unused?
       Write (bank 2) : CI - unknown? unused?
       Write (bank 3) : ATV2 - CD Audio Volume for Right-CD-Out to Right-SPU-Input
800317f4 - cdreg2 address
       Read (any bank): RDDATA - CD Data FIFO (can be byte or halfword read)
       Write (bank 0) : PARAMETER - CD Parameter FIFO
       Write (bank 1) : HINTMSK - CD Interrupt Enable Register
       Write (bank 2) : ATV0 - CD Audio Volume for Left-CD-Out to Left-SPU-Input
       Write (bank 3) : ATV3 - CD Audio Volume for Right-CD-Out to Left-SPU-Input
800317f8 - cdreg3 address
       Read (bank 0,2): HINTMSK - CD Interrupt Enable Register
       R/W (bank 1,3) : HINTSTS (read)/HCLRCTL (write) - CD Interrupt Flag Register
           (bank 3, bit 5): apply CD Audio Volume changes (... bit 5 on a byte?)
       Write (bank 0) : HCHPCTL - CD Request Register
       Write (bank 2) : ATV1 - CD Audio Volume for Left-CD-Out to Right-SPU-Input

80031b40 - HSTS (read)/ADDRESS (write) - CD Index/Status register
80031b44 - cdreg1 address
80031b48 - cdreg2 address
80031b4c - cdreg3 address
80031b50 - COM_DELAY - Common Delay
       0xffff 0000: unused (always 0x0000)
       0x0000 f000: COM3 - Strobe active-going edge delay
       0x0000 0f00: COM2 - Floating release cycles
       0x0000 00f0: COM1 - Hold period cycles
       0x0000 000f: COM0 - Recovery period cycles
80031b54 - SPU Voice IO Port

LIBCD

80031b74 - CDROM Delay/Size
       0x8000 0000: Wait (whether to wait for external device)
       0x4000 0000: Wide DMA (whether to use 32 bit data bus width)
       0x2000 0000: DMA Timing select (whether to override timing with 0x0f00 0000)
       0x1000 0000: Address error flag
       0x0f00 0000: DMA Timing override
       0x00f0 0000: always 0
       0x000f 0000: Number of address bits
       0x0000 c000: unknown
       0x0000 2000: Auto Increment
       0x0000 1000: Data Bus Width (0 = 8 bit, 1 = 16 bit, only if not 0x4000 0000)
       0x0000 0800: pre-strobe period (using COM3 timing)
       0x0000 0400: floating period (using COM2 timing)
       0x0000 0200: Hold Period (using COM1 timing)
       0x0000 0100: Recovery Period (using COM0 timing)
       0x0000 00f0: Read delay
       0x0000 000f: Write delay
80031b78 - DPCR - DMA Control Register
       Sets DMA priority to each DMA channel, 3 bits per priority, 1 bit for a master enable flag.
       Curiously, the CPU DMA channel has a master enable flag, but this doesn't impede the CPU's ability to access the CPU DMA channel.
80031b7c - DMA CDROM Base Address
       Contains the address the DMA should start reading from/write to.
       In this case, specifically to write files from the CDROM into RAM (opening them)
80031b80 - DMA CDROM Block Control
       Filesize of data to transfer over DMA, in words.
80031b84 - DMA CDROM Channel Control
       0x8000 0000: Unused
       0x4000 0000: Perform bus snooping
       0x2000 0000: Various effects per Transfer Mode (burst = pause transfer, other modes = stop 0x1000 0000 from being turned off every slice (undesired). doesn't do anything if transfer was caused by a DREQ.)
       0x1000 0000: Do not wait for DREQ (automatically off when transfer starts)
       0x0e00 0000: unused
       0x0100 0000: Start Transfer
       0x0080 0000: unused
       0x0070 0000: Chopping CPU window size
       0x0008 0000: unused
       0x0007 0000: Chopping DMA window size
       0x0000 0600: Transfer/Sync mode (0 = burst (all at once when acknowledged by DREQ), 1 = slice (cut transfer into multiple blocks, requires DREQ for every transfer), 2 = Linked List mode, 3 = reserved by...?)
       0x0000 0100: Various effects per Transfer Mode (burst = enable CPU to cycle steal, slice = hang DMA, linked list = transfer header before data?)
       0x0000 00fc: unused
       0x0000 0002: MADR increment per step (0 = +4, 1 = -4)
       0x0000 0001: transfer direction (0 = device to RAM, 1 = RAM to device)

80031b88 - some file structure?
80031b90 - starting address in RAM to load file to (
80031b94 - current address in RAM to load file to

80031ba0 - counter for number of sections of file to load?
80031ba4 - ??
80031ba8 - First LBA Sector of file to load
80031bac - Current LBA Sector of file to load

LIBCARD / Unidentifiable

80031bb8 - cdreg addresses (repeat 9 times; might be leftover logic for dealing with individual data banks? might be from another library.)

80031c48 - CDROM Delay/Size 
80031c4c - COM_DELAY - Common Delay
80031c50 - DPCR - DMA Control Register
80031c54 - DICR - DMA Interrupt Register
80031c58 - DMA MDECout channel control
80031c5c - DMA MDECout channel base address
80031c60 - DMA GPU channel control
80031c64 - DMA GPU base address
80031c68 - DMA CDROM channel control
80031c6c - DMA CDROM base address
80031c70 - DMA SPU channel control
80031c74 - DMA SPU base address
80031c78 - I_STAT - Interrupt status register
80031c7c - I_MASK - Interrupt mask register

00031c88 - HSTS (read)/ADDRESS (write) - CD Index/Status register
00031c8c - cdreg1
00031c90 - cdreg2 
00031c94 - cdreg3 
80031c98 - I_STAT - Interrupt status register
80031c9c - Dotclock Timer

80032964 - GP0 
80032968 - GP1 
8003296c - DMA GPU base address
80032970 - DMA GPU block control
80032974 - DMA GPU channel control
80032978 - DMA OTC base address
8003297c - DMA OTC block control
80032980 - DMA OTC channel control
80032984 - DPCR - DMA Control Register