Difference between revisions of "Disable DMA4 Channel"
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(Created page with "<font face='Courier New'> 000192ec: 3c058003 lui r5,0x8003 000192f0: 8ca5ad54 lw r5,-0x52ac(r5) 000192f4: 3c03fff8 lui r3,0xfff8 000192f8: 8ca20000 lw r2,0x0000(r5) 000...") |
m (Talcall moved page 000192ec - 00019348 to Disable DMA4 Channel) |
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<font face='Courier New'> | <font face='Courier New'> | ||
| − | + | stops DMA transfers to the SPU and changes that channel's priority | |
| + | p1 = mode | ||
| + | 0: set SPU DMA priority moderately low | ||
| + | !0: set SPU DMA priority moderately high | ||
| + | |||
000192ec: 3c058003 lui r5,0x8003 | 000192ec: 3c058003 lui r5,0x8003 | ||
| − | 000192f0: 8ca5ad54 lw r5,-0x52ac(r5) | + | 000192f0: 8ca5ad54 lw r5,-0x52ac(r5) # DMA control register |
000192f4: 3c03fff8 lui r3,0xfff8 | 000192f4: 3c03fff8 lui r3,0xfff8 | ||
| − | 000192f8: 8ca20000 lw r2,0x0000(r5) | + | 000192f8: 8ca20000 lw r2,0x0000(r5) # read from |
| − | 000192fc: 3463ffff ori r3,r3,0xffff | + | 000192fc: 3463ffff ori r3,r3,0xffff # 0xfff8 ffff |
| − | 00019300: 00431024 and r2,r2,r3 | + | 00019300: 00431024 and r2,r2,r3 # disable SPU DMA channel |
| − | 00019304: aca20000 sw r2,0x0000(r5) | + | 00019304: aca20000 sw r2,0x0000(r5) # give instruction |
| − | 00019308: 10800007 beq r4,r0,0x00019328 | + | 00019308: 10800007 beq r4,r0,0x00019328 # |
0001930c: 00000000 nop | 0001930c: 00000000 nop | ||
00019310: 3c028003 lui r2,0x8003 | 00019310: 3c028003 lui r2,0x8003 | ||
| − | 00019314: 8c42ad54 lw r2,-0x52ac(r2) | + | 00019314: 8c42ad54 lw r2,-0x52ac(r2) # DMA control register |
00019318: 00000000 nop | 00019318: 00000000 nop | ||
| − | 0001931c: 8c430000 lw r3,0x0000(r2) | + | 0001931c: 8c430000 lw r3,0x0000(r2) |
00019320: 080064cf j 0x0001933c | 00019320: 080064cf j 0x0001933c | ||
| − | 00019324: 3c040003 lui r4,0x0003 | + | 00019324: 3c040003 lui r4,0x0003 # set SPU DMA priority 3 |
| + | |||
00019328: 3c028003 lui r2,0x8003 | 00019328: 3c028003 lui r2,0x8003 | ||
| − | 0001932c: 8c42ad54 lw r2,-0x52ac(r2) | + | 0001932c: 8c42ad54 lw r2,-0x52ac(r2) # DMA control register |
00019330: 00000000 nop | 00019330: 00000000 nop | ||
00019334: 8c430000 lw r3,0x0000(r2) | 00019334: 8c430000 lw r3,0x0000(r2) | ||
| − | 00019338: 3c040005 lui r4,0x0005 | + | 00019338: 3c040005 lui r4,0x0005 # set SPU DMA priority 5 |
| − | 0001933c: 00641825 or r3,r3,r4 | + | 0001933c: 00641825 or r3,r3,r4 # set priority |
| − | 00019340: ac430000 sw r3,0x0000(r2) | + | 00019340: ac430000 sw r3,0x0000(r2) # give instruction |
00019344: 03e00008 jr r31 | 00019344: 03e00008 jr r31 | ||
00019348: 00000000 nop | 00019348: 00000000 nop | ||
</font> | </font> | ||
Latest revision as of 01:06, 22 January 2025
stops DMA transfers to the SPU and changes that channel's priority p1 = mode 0: set SPU DMA priority moderately low !0: set SPU DMA priority moderately high
000192ec: 3c058003 lui r5,0x8003 000192f0: 8ca5ad54 lw r5,-0x52ac(r5) # DMA control register 000192f4: 3c03fff8 lui r3,0xfff8 000192f8: 8ca20000 lw r2,0x0000(r5) # read from 000192fc: 3463ffff ori r3,r3,0xffff # 0xfff8 ffff 00019300: 00431024 and r2,r2,r3 # disable SPU DMA channel 00019304: aca20000 sw r2,0x0000(r5) # give instruction 00019308: 10800007 beq r4,r0,0x00019328 # 0001930c: 00000000 nop 00019310: 3c028003 lui r2,0x8003 00019314: 8c42ad54 lw r2,-0x52ac(r2) # DMA control register 00019318: 00000000 nop 0001931c: 8c430000 lw r3,0x0000(r2) 00019320: 080064cf j 0x0001933c 00019324: 3c040003 lui r4,0x0003 # set SPU DMA priority 3
00019328: 3c028003 lui r2,0x8003 0001932c: 8c42ad54 lw r2,-0x52ac(r2) # DMA control register 00019330: 00000000 nop 00019334: 8c430000 lw r3,0x0000(r2) 00019338: 3c040005 lui r4,0x0005 # set SPU DMA priority 5 0001933c: 00641825 or r3,r3,r4 # set priority 00019340: ac430000 sw r3,0x0000(r2) # give instruction 00019344: 03e00008 jr r31 00019348: 00000000 nop
