Difference between revisions of "Effect Related (0x1a1c90)"
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(Created page with " 801a1c90: 34030001 ori r3,r0,0x0001 801a1c94: 34020001 ori r2,r0,0x0001 801a1c98: 3c01801c lui r1,0x801c 801a1c9c: a420f02c sh r0,-0x0fd4(r1) 801a1ca0: 3c01801c lui r1,0x...") |
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| − | 801a1c90: 34030001 ori r3,r0,0x0001 | + | Initialise effect phases to queue 0, 1, 0, 0, 2, 0, 0, etc. |
| − | 801a1c94: 34020001 ori r2,r0,0x0001 | + | 801a1c90: 34030001 ori r3,r0,0x0001 1 |
| + | 801a1c94: 34020001 ori r2,r0,0x0001 1 | ||
801a1c98: 3c01801c lui r1,0x801c | 801a1c98: 3c01801c lui r1,0x801c | ||
| − | 801a1c9c: a420f02c sh r0,-0x0fd4(r1) | + | 801a1c9c: a420f02c sh r0,-0x0fd4(r1) queued executing phase = 0 (effect phase 0 data) |
801a1ca0: 3c01801c lui r1,0x801c | 801a1ca0: 3c01801c lui r1,0x801c | ||
| − | 801a1ca4: a4229158 sh r2,-0x6ea8(r1) | + | 801a1ca4: a4229158 sh r2,-0x6ea8(r1) next effect phase to execute = 1 |
801a1ca8: 00031140 sll r2,r3,0x05 | 801a1ca8: 00031140 sll r2,r3,0x05 | ||
801a1cac: 00431023 subu r2,r2,r3 | 801a1cac: 00431023 subu r2,r2,r3 | ||
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801a1cb4: 3c01801c lui r1,0x801c | 801a1cb4: 3c01801c lui r1,0x801c | ||
801a1cb8: 00220821 addu r1,r1,r2 | 801a1cb8: 00220821 addu r1,r1,r2 | ||
| − | 801a1cbc: a423f02e sh r3,-0x0fd2(r1) | + | 801a1cbc: a423f02e sh r3,-0x0fd2(r1) store current phase in temp effect data? |
| − | 801a1cc0: 24630001 addiu r3,r3,0x0001 | + | 801a1cc0: 24630001 addiu r3,r3,0x0001 ++ |
801a1cc4: 3c01801c lui r1,0x801c | 801a1cc4: 3c01801c lui r1,0x801c | ||
801a1cc8: 00220821 addu r1,r1,r2 | 801a1cc8: 00220821 addu r1,r1,r2 | ||
| − | 801a1ccc: a423f02c sh r3,-0x0fd4(r1) | + | 801a1ccc: a423f02c sh r3,-0x0fd4(r1) store queued phase to execute in phase currently initialising |
801a1cd0: 3c01801c lui r1,0x801c | 801a1cd0: 3c01801c lui r1,0x801c | ||
801a1cd4: 00220821 addu r1,r1,r2 | 801a1cd4: 00220821 addu r1,r1,r2 | ||
| − | 801a1cd8: ac20f120 sw r0,-0x0ee0(r1) | + | 801a1cd8: ac20f120 sw r0,-0x0ee0(r1) |
801a1cdc: 28620010 slti r2,r3,0x0010 | 801a1cdc: 28620010 slti r2,r3,0x0010 | ||
| − | 801a1ce0: 1440fff2 bne r2,r0,0x801a1cac | + | 801a1ce0: 1440fff2 bne r2,r0,0x801a1cac loop while phase to setup is less than 0x10? |
801a1ce4: 00031140 sll r2,r3,0x05 | 801a1ce4: 00031140 sll r2,r3,0x05 | ||
801a1ce8: 00431023 subu r2,r2,r3 | 801a1ce8: 00431023 subu r2,r2,r3 | ||
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801a1cf0: 3c01801c lui r1,0x801c | 801a1cf0: 3c01801c lui r1,0x801c | ||
801a1cf4: 00220821 addu r1,r1,r2 | 801a1cf4: 00220821 addu r1,r1,r2 | ||
| − | 801a1cf8: a420f02c sh r0,-0x0fd4(r1) | + | 801a1cf8: a420f02c sh r0,-0x0fd4(r1) store phase 0x10's queued phase as 0 |
801a1cfc: 3c01801c lui r1,0x801c | 801a1cfc: 3c01801c lui r1,0x801c | ||
801a1d00: 00220821 addu r1,r1,r2 | 801a1d00: 00220821 addu r1,r1,r2 | ||
801a1d04: a423f02e sh r3,-0x0fd2(r1) | 801a1d04: a423f02e sh r3,-0x0fd2(r1) | ||
801a1d08: 3c01801c lui r1,0x801c | 801a1d08: 3c01801c lui r1,0x801c | ||
| − | 801a1d0c: a420bf90 sh r0,-0x4070(r1) | + | 801a1d0c: a420bf90 sh r0,-0x4070(r1) Store currently executing phase = 0 |
801a1d10: 3c01801c lui r1,0x801c | 801a1d10: 3c01801c lui r1,0x801c | ||
801a1d14: a420f004 sh r0,-0x0ffc(r1) | 801a1d14: a420f004 sh r0,-0x0ffc(r1) | ||
Latest revision as of 05:45, 23 December 2022
Initialise effect phases to queue 0, 1, 0, 0, 2, 0, 0, etc.
801a1c90: 34030001 ori r3,r0,0x0001 1 801a1c94: 34020001 ori r2,r0,0x0001 1 801a1c98: 3c01801c lui r1,0x801c 801a1c9c: a420f02c sh r0,-0x0fd4(r1) queued executing phase = 0 (effect phase 0 data) 801a1ca0: 3c01801c lui r1,0x801c 801a1ca4: a4229158 sh r2,-0x6ea8(r1) next effect phase to execute = 1 801a1ca8: 00031140 sll r2,r3,0x05 801a1cac: 00431023 subu r2,r2,r3 801a1cb0: 000210c0 sll r2,r2,0x03 801a1cb4: 3c01801c lui r1,0x801c 801a1cb8: 00220821 addu r1,r1,r2 801a1cbc: a423f02e sh r3,-0x0fd2(r1) store current phase in temp effect data? 801a1cc0: 24630001 addiu r3,r3,0x0001 ++ 801a1cc4: 3c01801c lui r1,0x801c 801a1cc8: 00220821 addu r1,r1,r2 801a1ccc: a423f02c sh r3,-0x0fd4(r1) store queued phase to execute in phase currently initialising 801a1cd0: 3c01801c lui r1,0x801c 801a1cd4: 00220821 addu r1,r1,r2 801a1cd8: ac20f120 sw r0,-0x0ee0(r1) 801a1cdc: 28620010 slti r2,r3,0x0010 801a1ce0: 1440fff2 bne r2,r0,0x801a1cac loop while phase to setup is less than 0x10? 801a1ce4: 00031140 sll r2,r3,0x05 801a1ce8: 00431023 subu r2,r2,r3 801a1cec: 000210c0 sll r2,r2,0x03 801a1cf0: 3c01801c lui r1,0x801c 801a1cf4: 00220821 addu r1,r1,r2 801a1cf8: a420f02c sh r0,-0x0fd4(r1) store phase 0x10's queued phase as 0 801a1cfc: 3c01801c lui r1,0x801c 801a1d00: 00220821 addu r1,r1,r2 801a1d04: a423f02e sh r3,-0x0fd2(r1) 801a1d08: 3c01801c lui r1,0x801c 801a1d0c: a420bf90 sh r0,-0x4070(r1) Store currently executing phase = 0 801a1d10: 3c01801c lui r1,0x801c 801a1d14: a420f004 sh r0,-0x0ffc(r1) 801a1d18: 3c01801b lui r1,0x801b 801a1d1c: ac2063e8 sw r0,0x63e8(r1) 801a1d20: 03e00008 jr r31 801a1d24: 00000000 nop
