Difference between revisions of "Enable SPU IRQ EvCB"
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m (Talcall moved page Enable Root Counter 2 EvCB to Enable SPU IRQ EvCB) |
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| Line 5: | Line 5: | ||
00017c00: 27bdffe8 addiu r29,r29,0xffe8 | 00017c00: 27bdffe8 addiu r29,r29,0xffe8 | ||
00017c04: 30620001 andi r2,r3,0x0001 | 00017c04: 30620001 andi r2,r3,0x0001 | ||
| − | 00017c08: 14400008 bne r2,r0,0x00017c2c # end if | + | 00017c08: 14400008 bne r2,r0,0x00017c2c # end if SPU IRQ event already enabled |
00017c0c: afbf0010 sw r31,0x0010(r29) | 00017c0c: afbf0010 sw r31,0x0010(r29) | ||
00017c10: 3c048003 lui r4,0x8003 | 00017c10: 3c048003 lui r4,0x8003 | ||
| Line 11: | Line 11: | ||
00017c18: 34620001 ori r2,r3,0x0001 | 00017c18: 34620001 ori r2,r3,0x0001 | ||
00017c1c: 3c018003 lui r1,0x8003 | 00017c1c: 3c018003 lui r1,0x8003 | ||
| − | 00017c20: a4222a54 sh r2,0x2a54(r1) # set | + | 00017c20: a4222a54 sh r2,0x2a54(r1) # set SPU IRQ event enabled |
00017c24: 0c0087ed jal 0x00021fb4 # [[EnableEvent]] | 00017c24: 0c0087ed jal 0x00021fb4 # [[EnableEvent]] | ||
00017c28: 00000000 nop | 00017c28: 00000000 nop | ||
Revision as of 04:17, 4 February 2025
00017bf8: 3c038003 lui r3,0x8003 00017bfc: 94632a54 lhu r3,0x2a54(r3) # encoded instruction byte 00017c00: 27bdffe8 addiu r29,r29,0xffe8 00017c04: 30620001 andi r2,r3,0x0001 00017c08: 14400008 bne r2,r0,0x00017c2c # end if SPU IRQ event already enabled 00017c0c: afbf0010 sw r31,0x0010(r29) 00017c10: 3c048003 lui r4,0x8003 00017c14: 8c842a5c lw r4,0x2a5c(r4) # root counter 2 event 00017c18: 34620001 ori r2,r3,0x0001 00017c1c: 3c018003 lui r1,0x8003 00017c20: a4222a54 sh r2,0x2a54(r1) # set SPU IRQ event enabled 00017c24: 0c0087ed jal 0x00021fb4 # EnableEvent 00017c28: 00000000 nop 00017c2c: 8fbf0010 lw r31,0x0010(r29) 00017c30: 27bd0018 addiu r29,r29,0x0018 00017c34: 03e00008 jr r31 00017c38: 00000000 nop
