OPEN.BIN LIBPRESS timeout
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00073a6c: 27bdffd8 addiu r29,r29,0xffd8 00073a70: 00802821 addu r5,r4,r0 00073a74: 3c048006 lui r4,0x8006 00073a78: 248470e0 addiu r4,r4,0x70e0 "%s timeout:" 00073a7c: afbf0024 sw r31,0x0024(r29) 00073a80: 0c0088cb jal 0x0002232c printf <- this never returns? at least that's what ghidra tells me 00073a84: afb00020 sw r16,0x0020(r29) 00073a88: 3c048006 lui r4,0x8006 00073a8c: 24847080 addiu r4,r4,0x7080 " DMA=(%d,%d), ADDR=(0x%08x->0x%08x)" <- yes, the tab is a character here. 00073a90: 3c028007 lui r2,0x8007 00073a94: 8c4241b4 lw r2,0x41b4(r2) MDEC1 status 00073a98: 3c038007 lui r3,0x8007 00073a9c: 8c634188 lw r3,0x4188(r3) DMA MDEC IN channel control 00073aa0: 8c500000 lw r16,0x0000(r2) check MDEC1 status 00073aa4: 8c650000 lw r5,0x0000(r3) check DMA MDEC IN channel control status 00073aa8: 3c028007 lui r2,0x8007 00073aac: 8c424194 lw r2,0x4194(r2) DMA MDEC OUT channel control 00073ab0: 3c038007 lui r3,0x8007 00073ab4: 8c634180 lw r3,0x4180(r3) DMA MDEC IN base address 00073ab8: 00052e02 srl r5,r5,0x18 00073abc: 8c460000 lw r6,0x0000(r2) check DMA MDEC OUT channel control status 00073ac0: 3c028007 lui r2,0x8007 00073ac4: 8c42418c lw r2,0x418c(r2) DMA MDEC OUT base address 00073ac8: 30a50001 andi r5,r5,0x0001 print if bus snooping? 00073acc: 8c420000 lw r2,0x0000(r2) check DMA MDEC OUT base address 00073ad0: 00063602 srl r6,r6,0x18 00073ad4: afa20010 sw r2,0x0010(r29) print DMA MDEC OUT base address 00073ad8: 8c670000 lw r7,0x0000(r3) print DMA MDEC IN base address 00073adc: 0c0088cb jal 0x0002232c printf <- this never returns? 00073ae0: 30c60001 andi r6,r6,0x0001 print if bus snooping? 00073ae4: 3c048006 lui r4,0x8006 00073ae8: 248470a8 addiu r4,r4,0x70a8 " FIFO=(%d,%d),BUSY=%d,DREQ=(%d,%d),RGB24=%d,STP=%d" <- yes, another tab. 00073aec: 00102827 nor r5,r0,r16 get everything the current MDEC status *isn't* 00073af0: 00052fc2 srl r5,r5,0x1f print if MDEC FIFO is empty 00073af4: 00103782 srl r6,r16,0x1e 00073af8: 30c60001 andi r6,r6,0x0001 print if MDEC FIFO is full 00073afc: 00103f42 srl r7,r16,0x1d 00073b00: 30e70001 andi r7,r7,0x0001 print if MDEC is busy 00073b04: 00101702 srl r2,r16,0x1c 00073b08: 30420001 andi r2,r2,0x0001 00073b0c: afa20010 sw r2,0x0010(r29) print if MDEC0 ready to receive data 00073b10: 001016c2 srl r2,r16,0x1b 00073b14: 30420001 andi r2,r2,0x0001 00073b18: afa20014 sw r2,0x0014(r29) print if MDEC1 ready to send data 00073b1c: 00101642 srl r2,r16,0x19 00073b20: 30420001 andi r2,r2,0x0001 00073b24: 001085c2 srl r16,r16,0x17 00073b28: 32100001 andi r16,r16,0x0001 00073b2c: afa20018 sw r2,0x0018(r29) print if bit depth is either 8bit or 15bit 00073b30: 0c0088cb jal 0x0002232c printf <- this never returns? 00073b34: afb0001c sw r16,0x001c(r29) print if bit depth is 15bit 00073b38: 3c038007 lui r3,0x8007 00073b3c: 8c6341b4 lw r3,0x41b4(r3) MDEC1 status reg 00073b40: 3c028000 lui r2,0x8000 00073b44: ac620000 sw r2,0x0000(r3) instruct reset MDEC 00073b48: 3c028007 lui r2,0x8007 00073b4c: 8c424188 lw r2,0x4188(r2) DMA MDEC IN channel control 00073b50: 00000000 nop 00073b54: ac400000 sw r0,0x0000(r2) turn off 00073b58: 3c028007 lui r2,0x8007 00073b5c: 8c424194 lw r2,0x4194(r2) DMA MDEC OUT channel control 00073b60: 00000000 nop 00073b64: ac400000 sw r0,0x0000(r2) turn off 00073b68: 00001021 addu r2,r0,r0 00073b6c: 3c038007 lui r3,0x8007 00073b70: 8c634194 lw r3,0x4194(r3) DMA MDEC OUT channel control 00073b74: 3c048007 lui r4,0x8007 00073b78: 8c8441b4 lw r4,0x41b4(r4) MDEC status reg 00073b7c: 8c630000 lw r3,0x0000(r3) grab status reg 00073b80: 3c036000 lui r3,0x6000 00073b84: ac830000 sw r3,0x0000(r4) re-enable data in and data out requests 00073b88: 8fbf0024 lw r31,0x0024(r29) 00073b8c: 8fb00020 lw r16,0x0020(r29) 00073b90: 27bd0028 addiu r29,r29,0x0028 00073b94: 03e00008 jr r31 return 0 00073b98: 00000000 nop
